I couldn't find a post that specifically answers my question, and I am familiar enough with the documentation that I think I can make a safe guess--however I just want to put this out there as a sanity check to make sure I've got this straight.
I want to generate a clock on a TMP2 or 3_OUT pin and I need to know what the max frequency is that I can do. I am planning on using TMP2/3 since it appears to be on the ASYNC3 PLL output (/2 of system clock) as opposed to TMP1/2 which are on the AUXCLK (just the crystal frequency). Is this correct? (sanity check #1)
Next, according to table 5-132 in SPRS590D, the output would appear to be restricted to 4P high + 4P low, or a maximum frequency of 1/8P. However, section 2.6, Table 6 of SPRUFM5A indicates that the maximum clock frequency is just a /2 of the source clock (ASYNC3 in my case), assuming that the PRD register can be set to 1 (nothing seems to indicate otherwise, sanity check #2.
So given that the above statements are true, I could safely generate a 25MHz output clock from one of theTMP2/3 output pins with a 100MHz system clock, true or false?
Thanks