OMAP4 GPMC DMA Transfer

Hi Vijay,

There are some differences in the OMAP3 and OMAP4 DMA module, mainly DMA module has 3 ports in OMAP4 (read, write and configuration), when there are only 2 on OMAP3, so if you are trying to use the same driver it won't work almost for sure. For more reference you can see the TRM ie for 4430 (http://focus.ti.com/pdfs/wtbu/OMAP4430_ES2.x_Public_TRM_vK.zip)

If you need more help, can you describe little more what you are trying to do in the driver and the steps are you doing to configure it?

Hi

Yes I missing something on the DMA configuration part. I have gone through the TRM and I see there is WUGEN module added for 4430.

I am using Software DMA transfer, by setting DMA parameters for Write and Read (same like Nand Driver using DMA) and starting the DMA.  The portion of code I am using is here:

Firstly I am requesting DMA channel using dma_request() method. Then while transfer I m using the below transfer func().

----------------------------------------------------------------------------------------------------------------------------------------------------------

transfer_func( )

{

dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
        if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
                dev_err(&info->pdev->dev,
                        "Couldn't DMA map a %d byte buffer\n", len);
                goto out_copy;
        }

        if (is_write) {
            omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
                                                info->phys_base, 0, 0);
            omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
                                                        dma_addr, 0, 0);
            omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
                                        0x10, buf_len, OMAP_DMA_SYNC_FRAME,
                                        OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
        } else {
            omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
                                                info->phys_base, 0, 0);
            omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
                                                        dma_addr, 0, 0);
            omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
                                        0x10, buf_len, OMAP_DMA_SYNC_FRAME,
                                        OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
        }

         init_completion(&info->comp);

        omap_start_dma(info->dma_ch);

        /* setup and start DMA using dma_addr */
        wait_for_completion(&info->comp);

} //tranfer_func

This works for OMAP3.  Suggest me as what I am missing for 4430 ?

Thanks

Vijay

Hi Vijay,

Are you seeing the transfer_func to be call?, or at what point is the issue?, as you know is hard to help without debugging the issue.

It could help if you can provide little more details, as the scenario you are trying, points are working and maybe dump some register whit omapconf tool.

Also you can take a look to the driver is working: drivers/mtd/nand/omap2.c

Hi Israel

The transfer function is called. The issue is after the DMA is configured and started,  data transfer is not happening and no GPMC_CLK and CS signals  on the Logic Analyzer.

For all the dma transfer parameters set for write & read transfer, I printed the DMA registers and checked, they are proper. In this scenario, I have not connected the physical FPGA on GPMC pins, instead I am writing using DMA and checking the GPMC signals (Data, Add, CLK, CS, OE, WE) using Logic Analyzer. Also I referred to drivers/mtd/nand/omap2.c  and the same driver works for OMAP3 platform. The issue is on OMAP4 (Pandaboard)

Steps I followed:

1. Configured CS1 chip select in Mux Mode

2. In U-boot for CS1 Chip select configuration:

a. CS1 is configured with the gpmc timing values into CONFIG1...CONFIG7 registers.

b.  Setting CONTROL_CORE_PAD0_GPMC_NWP_PAD1_GPMC_CLK 24th bit to 1 to synchronize the sampling of the memeory signals

c. By default the GPMC data, adress and control lines are not enabled for gpmc on J3 and J6 connectors for panda board. So enabled muxing for all GPMC data, adress and control pins in U-boot

3. In Non-DMA mode, i,e without using DMA I do raw write & read and can see the signals observed on LA. So I am assuming Step 1 & 2 configuration is working.

4 . In DMA mode, DMA channel is requested and DMA configured and started. No Signals observed. ( As I said earlier the same works on OMAP3, but Chip select configured in Non-Mux mode )

Please let me know as what I am missing here ?

Thanks

Vijaydeep

Hi Israel

Any inputs from your end on the DMA configuration, as what I am missing here ?

Thanks

Vijaydeep.G

Hi Vijay,

There is a tool named omapconf, can you dump the gpmc and dma configuration registers with that tool and attach them?

I have been looking at this and seems to be ok at least the transfer function, but I have doubts about the channel (info->dma_ch), can you print it's value?

Hi

On OMAP4,  OMAP24XX_DMA_GPMC is used as DMA trigger in omap_request_dma()  for requesting the channel ( channel 0 or 1 assigned for the transfer) and  in omap_set_dma_transfer_params()  for  setting DMA transfer. Then I don't see the DMA callback getting called and and its  unable to finish the DMA transfer ? As said above, no GPMC signals observed on Logic Analyzer.

I have print the value of  variable (info->dma_ch) channel and the value is 0 or 1. Most of the time Channel 1 is assigned.

For OMAP4, Is there anything extra configuration has to be done for DMA transfer over GPMC Interface ?

Can anyone highlight difference in GPMC DMA Configuration & Transfer functionality over OMAP3 (DM3730) and OMAP4(Pandaboard) ?

Regards,

Vijaydeep

What I see is that some register has change, look at:

GPMC_PREFETCH_CONTROL
GPMC_PREFETCH_CONFIG1
GPMC_PREFETCH_CONFIG2

ie: GPMC_PREFETCH_CONFIG1[2] DMAMODE Select either DMA synchronized mode or software manual mode.

That bit is not in omap3

Did you update your driver to have that kind of changes?

Hi  Israel

I have configured GPMC chip select CS1 as NOR flash interface in Synchronous mode.

I think prefetch register will be used when GPMC Chip select CS1 is configured as Nand interface.

Anyways, I have got the address of register GPMC_PREFETCH_CONFIG2 as 0x500001E0 from OMAP4 TRM. I have read the register value and set the GPMC_PREFETCH_CONFIG1[2] DMAMODE ( bit 2) as 0x1: DMA request synchronization is enabled. A DMA request protocol is used.
---------------------------------------------------------

a.Initial Value

./devmem 0x500001E0
Value at address 0x500001E0 (0x401141e0): 0x4000

b. Set GPMC_PREFETCH_CONFIG1[2] DMAMODE ( bit 2) as 0x1

./devmem 0x500001E0 w 0x4004

Value at address 0x500001E0 (0x401141e0): 0x4004

----------------------------------------------------------------------------------------------

But still after setting the GPMC_PREFETCH_CONFIG1[2] DMAMODE as DMA synchronized mode, DMA transfer is not happening. Is there anything else I am missing ?

Thanks

Vijay

Hi Vijay,

In your transfer_func you are missing some configuration for the gpmc like threshold, look at drivers/mtd/nand/omap2.c@omap_nand_dma_transfer:

    /*  configure and start prefetch transfer */
    ret = gpmc_prefetch_enable(info->gpmc_cs,
            PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);

My guess is that you are configuring DMA and GPMC separately, but you never configure the relation between the two like that function is doing. So I went back to you transfer_func and saw you are not doing the same that in the omap-nand driver.

Please let me know if that fix your issue.

Hi Israel

I am configuring GPMC as NOR interface. So I think I do not need to configure Prefetch engine, since I have done the same on OMAP3 GPMC using DMA and it works.

Its clear from TRM that PREFETCH engine needs to configured for NAND interface.

Is my thinking right ?

Regards,

Vijay

Hi Vijay,

Yes, if you are using NOR interface you don't need prefetch.

I think for this issue it would be better if you review if your driver meets the steps at chapter 15.4.5 GPMC Basic Programming Model from TRM

Hi Israel

Yes I have referred TRM Nor programming model. Are there any  GPMC DMA (NOR )driver references for OMAP4 platform  in Android ?

Regards,

Vijay

Hi, if you have a working example, can you post the link?  or code?

thanks,

Vincent

Hi Vijay,

I am also interested in DMA with GPMC . I have connected FPGA to GPMC port of omap 3530 (Gumstix Overo)

And tested Read Write Operation. Now I want to complete the reading procedure through DMA.

I never used DMA so unable to get start, can you plese share your code for DMA which reads Data from GPMC.

Nilesh Mane