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AM67: DDRSS config for >85C

Hisao Uchikoshi
Genius 15480 points

Part Number: AM67
Other Parts Discussed in Thread: SYSCONFIG

Hi Experts,

My customer is asking about DDRSS config. My customer generates .dtsi file by enabling with below option. 

image.png

The question is how customer can confirm the output file is expected without the detail register information? Shoud we ask customer to trust it?

Below is the diff file between enabling >85 and disabling >85. Could you please check it?

diff --git a/k3-j722s-ddr-evm-lp4_3733_2GB_ExtendTemp.dtsi b/k3-j722s-ddr-evm-lp4_3733_2GB_NormalTemp.dtsi
index b64aa6f..b666bcd 100644
--- a/k3-j722s-ddr-evm-lp4_3733_2GB_ExtendTemp.dtsi
+++ b/k3-j722s-ddr-evm-lp4_3733_2GB_NormalTemp.dtsi
@@ -63,12 +63,12 @@
 #define DDRSS_CTL_47_DATA 0x00000800
 #define DDRSS_CTL_48_DATA 0x09090004
 #define DDRSS_CTL_49_DATA 0x00000204
-#define DDRSS_CTL_50_DATA 0x007A0012
-#define DDRSS_CTL_51_DATA 0x09140054
-#define DDRSS_CTL_52_DATA 0x00003A26
-#define DDRSS_CTL_53_DATA 0x007A0012
-#define DDRSS_CTL_54_DATA 0x09140054
-#define DDRSS_CTL_55_DATA 0x09003A26
+#define DDRSS_CTL_50_DATA 0x0072000F
+#define DDRSS_CTL_51_DATA 0x09140050
+#define DDRSS_CTL_52_DATA 0x00003A22
+#define DDRSS_CTL_53_DATA 0x0072000F
+#define DDRSS_CTL_54_DATA 0x09140050
+#define DDRSS_CTL_55_DATA 0x09003A22
 #define DDRSS_CTL_56_DATA 0x000A0A09
 #define DDRSS_CTL_57_DATA 0x0400036D
 #define DDRSS_CTL_58_DATA 0x090F2005
@@ -79,11 +79,11 @@
 #define DDRSS_CTL_63_DATA 0x0E007FE6
 #define DDRSS_CTL_64_DATA 0x0304200F
 #define DDRSS_CTL_65_DATA 0x04050002
-#define DDRSS_CTL_66_DATA 0x24262426
+#define DDRSS_CTL_66_DATA 0x24232423
 #define DDRSS_CTL_67_DATA 0x01010008
-#define DDRSS_CTL_68_DATA 0x044A4A08
-#define DDRSS_CTL_69_DATA 0x042B2B04
-#define DDRSS_CTL_70_DATA 0x00002B2B
+#define DDRSS_CTL_68_DATA 0x04464608
+#define DDRSS_CTL_69_DATA 0x04282804
+#define DDRSS_CTL_70_DATA 0x00002828
 #define DDRSS_CTL_71_DATA 0x00000101
 #define DDRSS_CTL_72_DATA 0x00000000
 #define DDRSS_CTL_73_DATA 0x01000000
@@ -103,8 +103,8 @@
 #define DDRSS_CTL_87_DATA 0x03004000
 #define DDRSS_CTL_88_DATA 0x00001201
 #define DDRSS_CTL_89_DATA 0x000E0005
-#define DDRSS_CTL_90_DATA 0x2908000E
-#define DDRSS_CTL_91_DATA 0x0A050529
+#define DDRSS_CTL_90_DATA 0x2608000E
+#define DDRSS_CTL_91_DATA 0x0A050526
 #define DDRSS_CTL_92_DATA 0x1B0E0A03
 #define DDRSS_CTL_93_DATA 0x1B0E0A04
 #define DDRSS_CTL_94_DATA 0x04010104
@@ -696,15 +696,15 @@
 #define DDRSS_PI_245_DATA 0x00000315
 #define DDRSS_PI_246_DATA 0x20010004
 #define DDRSS_PI_247_DATA 0x0A0A0A03
-#define DDRSS_PI_248_DATA 0x2B0F0000
-#define DDRSS_PI_249_DATA 0x24140026
+#define DDRSS_PI_248_DATA 0x280F0000
+#define DDRSS_PI_249_DATA 0x24140023
 #define DDRSS_PI_250_DATA 0x0000731B
-#define DDRSS_PI_251_DATA 0x20070054
+#define DDRSS_PI_251_DATA 0x20070050
 #define DDRSS_PI_252_DATA 0x1B131B1C
-#define DDRSS_PI_253_DATA 0x2B0F0000
-#define DDRSS_PI_254_DATA 0x24140026
+#define DDRSS_PI_253_DATA 0x280F0000
+#define DDRSS_PI_254_DATA 0x24140023
 #define DDRSS_PI_255_DATA 0x0000731B
-#define DDRSS_PI_256_DATA 0x20070054
+#define DDRSS_PI_256_DATA 0x20070050
 #define DDRSS_PI_257_DATA 0x1B131B1C
 #define DDRSS_PI_258_DATA 0x00000000
 #define DDRSS_PI_259_DATA 0x000000B2

Below is the header of .dtsi.

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
 * This file was generated with the following tool revisions:
 *     - SysConfig: Revision 1.26.2+4477
 *     - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0
 * This file was generated on Tue Feb 03 2026 11:59:02 GMT+0900
*/

If you need any information, please let us know.

Regards,

Uchikoshi

  • 0
    TI__Mastermind 43370 points

    Hi,

    Registers are provided with the AM67x TRM. https://www.ti.com/lit/zip/sprujb3 

    For J722S family of devices (AM67), the DDR tool (version 0.12.0) input parameter "Max Operating Temperature" controls whether de-rating is automatically added to the required parameters for high temperature operation: tDQSCK(max), tRCD, tRC, tRAS(min), tRP, and tRRD.

    It does not change refresh rate (though the tool already defaults to a refresh rate of 1.95 us). 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Genius 15480 points

    Hi Kevin,

    How can we confirm if the refresh rate is not changed? Customer is saying the register setting >85C becomes a half of that of <85C.

    Below is the diff of the register settings between >85 and <85. Is it good enough?

    >85 ＜85 Delta
    DDRSS_CTL_50_DATA 0x007A0012 0x0072000F TRC_F1 : 7A vs 72, TRRD_F1 : 12 vs 0F
    DDRSS_CTL_51_DATA 0x09140054 0x09140050 TRAS_MIN_F1 : 54 vs 50
    DDRSS_CTL_52_DATA 0x00003A26 0x00003A22 TRP_F1 : 26 vs 22
    DDRSS_CTL_53_DATA 0x007A0012 0x0072000F TRC_F2 : 7A vs 72, TRRD_F2 : 12 vs F
    DDRSS_CTL_54_DATA 0x09140054 0x09140050 TRAS_MIN_F2 : 54 vs 50
    DDRSS_CTL_55_DATA 0x09003A26 0x09003A22 TRP_F2 : 26 vs 23
    DDRSS_CTL_66_DATA 0x24262426 0x24232423 TRCD_F2 : 26 vs 23, TRCD_F1 : 26 vs 23
    DDRSS_CTL_68_DATA 0x044A4A08 0x04464608 TDAL_F2 : 4A vs 46, TDAL_F1 : 4A vs 46
    DDRSS_CTL_69_DATA 0x042B2B04 0x04282804 TRP_AB_F2_0 : 2B vs 28, TRP_AB_F1_0 : 2B vs 28
    DDRSS_CTL_70_DATA 0x00002B2B 0x00002828 TRP_AB_F2_1 : 2B vs 28, TRP_AB_F1_1 : 2B vs 28
    DDRSS_CTL_90_DATA 0x2908000E 0x2608000E TMRRI_F1 : 29 vs 26
    DDRSS_CTL_91_DATA 0x0A050529 0x0A050526 TMRRI_F2 : 29 vs 26
    DDRSS_PI_248_DATA 0x2B0F0000 0x280F0000 PI_TRTP_F1 :  2B vs 28 
    DDRSS_PI_249_DATA 0x24140026 0x24140023 PI_TRCD_F1 :  26 vs 23
    DDRSS_PI_251_DATA 0x20070054 0x20070050 PI_TRAS_MIN_F1 : 54 vs 50
    DDRSS_PI_253_DATA 0x2B0F0000 0x280F0000 PI_TRTP_F2 : 2B vs 28
    DDRSS_PI_254_DATA 0x24140026 0x24140023 PI_TRCD_F2 : 26 vs 23
    DDRSS_PI_256_DATA 0x20070054 0x20070050 PI_TRAS_MIN_F2 : 54 vs 50
  • 0 in reply to Hisao Uchikoshi
    TI__Mastermind 43370 points

    Hi,

    Hisao Uchikoshi said:
    How can we confirm if the refresh rate is not changed?

    The refresh rate is determined by the tREFI input parameter (shown below). The user can set this parameter as required by their system. As previously indicated, it is not impacted by the "Max Operating Temperature" tool input parameter.

    Hisao Uchikoshi said:
    Below is the diff of the register settings between >85 and <85. Is it good enough?

    I am not sure what you mean by "is it good enough?". As previously indicated, for J722S family of devices (AM67), the DDR tool (version 0.12.0) input parameter "Max Operating Temperature" controls whether de-rating is automatically added to the required parameters for high temperature operation: tDQSCK(max), tRCD, tRC, tRAS(min), tRP, and tRRD. The customer is responsible for configuring the refresh rate as needed for their system.

    Regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Genius 15480 points

    Hi Kevin,

    Kevin S said:
    The customer is responsible for configuring the refresh rate as needed for their system.

    My customer is expecting if the temperature is higher than 85C, DDRSS can modify the refresh rate automatically. Is it possible? 

  • 0 in reply to Hisao Uchikoshi
    TI__Mastermind 43370 points

    Hi,

    Changing the refresh rate dynamically would require software support. 

    The DDR controller can poll MR4 automatically and generate an interrupt, but software would need to modify the refresh rate accordingly. 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Genius 15480 points

    Hi Kevin,

    Thank you for your answer. I heard that we may support the driver for auto refresh rate control. How can we get it?

  • 0 in reply to Hisao Uchikoshi
    TI__Mastermind 43370 points

    Hi,

    As far as I am aware, this may not be supported in the SDK. 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Genius 15480 points

    Hi Kevin,

    I might misunderstand about below.

    Kevin S said:
    The DDR controller can poll MR4 automatically and generate an interrupt, but software would need to modify the refresh rate accordingly. 

    DDR sysconfig tool for AM62 supports below configuration for MR2 and MR4 but that for AM67 does not support it. 

    Does this mean AM67 DDRSS does not poll MR4? Or is above configuration the different function?

    The customer uses DDR in environments above 85°C, should the tREFIab value be set to a refresh rate of 85°C or higher? And does the customer need to create software to read MR4 and change the auto refresh rate if necessary?

    In addition to the DDRSS register settings output by Sysconfig, what other work should the customer create other than evaluation? 

  • 0 in reply to Hisao Uchikoshi
    TI__Mastermind 43370 points

    Hi ,

    From a hardware perspective, the AM67 DDR controller has the capability to poll MR4 periodically and generate an interrupt when a change in the MR4 value occurs.

    From a tool perspective, AM67 is sourced from the TDA4x_DRA8x_AM67x-AM69x_DDR_Config tool, which has support to enable MR4 polling for the following family of devices: J721E, J7200, J721S2, and J784S4. Since AM67 belongs to the J722S family of devices, the tool does not currently support MR4 polling. Adding support is something we could address in a future release.

    Hisao Uchikoshi said:
    And does the customer need to create software to read MR4 and change the auto refresh rate if necessary?

    Software is required to actually change the refresh rate. Hardware only polls MR4 from the LPDDR4 memory, it does not actually modify the interval at which refresh commands are issued.

    Regards,
    Kevin