Part Number: AM6442
I have a custom PCB that I designed that has an AM6442 SoC on it.
In the AM6442 TRM (SPRUIM2H) Table 12-3591 (page 8900) it says that when the HIGH_SPEED_ENA bit is set to zero then the data/cmd lines should output on the falling edge of the bus clock. But when I measure on an oscilloscope, the data always appears relative to the rising edge regardless of the state of HIGH_SPEED_ENA.
Because data/cmd output on the rising edge of the clock, during initial configuration of the eMMC it appears that I get setup/hold violations when running the bus clock at 400kHz in open drain mode.
Is this bit (HIGH_SPEED_ENA) non-functional, or are there some other register bits in MMCSD0 that override it that I am not aware of?
During initial setup of an eMMC chip the eMMC spec (JESD84-B51) mandates that we start the host controller at 400kHz bus clock and in open drain mode. In open drain mode the output timing is heavily influenced by the external capacitance an resistance on the bus. For example 20pF capacitance and 10K pullups result in 200ns time constants.
The internal DLLs in the AM6442 can adjust the timing of CMD/DAT relative to the rising edge of the bus clock, but the adjustment range is small (like 20ns max). 20ns adjustment is insufficient to guarantee setup/hold timing when you are dealing with signals that have rise time > 200ns. Therefore I need the ability to output the cmd/data on the falling clock edge when in open drain mode or else I don't see how I can avoid setup/hold violations.
Any help you can give would be appreciated.
