Please answer following questions of AM335x from customer.
Q1:
<Customer>
Can L1 and L2 cache use as RAM and sot re any instruction?
I read the "ARM DDI 0344K (ID060510)Technical reference", but
no explanation that L1/L2 can configure as RAM, so I think L1 and L2 can use only cache.
Please confirm if my understanding is correct.
Q2:
<Customer>
Please advice required access cycles(latency) of L2 cache.
"ARM DDI 0344K (ID060510)Technical reference" 7.2 Cache organization
explains the L1 access cycle as follows.
"Both the instruction cache and the data cache are capable of
providing two words per cycle for all requesting sources."
But L2 has no explanation about access cycle.
Please advice how many CPU cycles are required in case of L1 miss and L2 hit.
Q3:
<Customer>
Pleas advice access cycle(latency) of internal RAM
AM335x has two 64KB internal RAM.(64KB in CPU Subsystem and 64 KB General-Purpose On-Chip Memory)
Please advice required CPU cycles when A8 core access these RAM.
Regards.