I'm reading about non-bursting peripheral servicing in the eDMA controller and there are some things I don't understand.
Suppose the goal is to hook it up to one of the UARTs (receive only for now), dealing with just receive mode for now. Correct me if I'm wrong about any of this.
SRC: UART receive data address (RHR)
DST: start of your destination somewhere in DRAM
BCNT: 0x100 (256 byte destination buffer)
ACNT: 1 (fetches one at a time)
Every time a UART receive event occurs, this triggers the DMA transfer of one byte. (or does it always have to be 32-bit words?)
Things I don't understand:
- What causes SRC to always reset back to the same address? With every transfer, DST should increment but SRC should always point to RHR
- How exactly does the condition get cleared? Is it just by reading the RHR?
- Could you safely have a second event source stop everything early? Suppose for instance you want to make a large (say 1 MB) UART receive buffer, and you want the kernel driver to be notified when that buffer gets full OR some timeout expired. Can you do that?
- Can you use this eDMA peripheral servicing technique on something more complicated like DCAN, where you don't clear the event by simply reading (but have to do something else, like release the message buffer)?
--Chris