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Interrupt Handler not firing on AM3517

I am trying to get the interrupt handling going on the AM3517 Cortex A8. I have laid out the ARM_Vectors using the scatter file at the addresses specified by the manual. But, when the code crashed on GDB instead of going into one of these handlers 
it shows me something like this  0x00014010 in ?? ()
I am attaching the disassembly for the section in question. Can someone help me out here ??
Disassembly of section ER_RAM_RO:

4020ffc0 <ARM_Vectors>:
4020ffc0: baadf00d blt 3ed8bffc <SRAM_OFFSET1+0x3eb8bffc>

4020ffc4 <RESET_VECTOR>:
PAD_VECTOR:
.word 0xbaadf00d

@ RESET
RESET_VECTOR:
b UNDEF_VECTOR
4020ffc4: eaffffff b 4020ffc8 <UNDEF_VECTOR>

4020ffc8 <UNDEF_VECTOR>:

@ UNDEF INSTR
UNDEF_VECTOR:
ldr pc, UNDEF_SubHandler_Trampoline
4020ffc8: e59ff010 ldr pc, [pc, #16] ; 4020ffe0 <UNDEF_SubHandler_Trampoline>

4020ffcc <SWI_VECTOR>:
4020ffcc: baadf00d blt 3ed8c008 <SRAM_OFFSET1+0x3eb8c008>

4020ffd0 <PREFETCH_VECTOR>:
SWI_VECTOR:
.word 0xbaadf00d

@ PREFETCH ABORT
PREFETCH_VECTOR:
ldr pc, ABORTP_SubHandler_Trampoline
4020ffd0: e59ff00c ldr pc, [pc, #12] ; 4020ffe4 <ABORTP_SubHandler_Trampoline>

4020ffd4 <DATA_VECTOR>:

@ DATA ABORT
DATA_VECTOR:
ldr pc, ABORTD_SubHandler_Trampoline
4020ffd4: e59ff00c ldr pc, [pc, #12] ; 4020ffe8 <ABORTD_SubHandler_Trampoline>

4020ffd8 <USED_VECTOR>:
4020ffd8: baadf00d blt 3ed8c014 <SRAM_OFFSET1+0x3eb8c014>

4020ffdc <IRQ_VECTOR>:
USED_VECTOR:
.word 0xbaadf00d

@ IRQ
IRQ_VECTOR:
ldr pc, IRQ_SubHandler_Trampoline
4020ffdc: e59ff008 ldr pc, [pc, #8] ; 4020ffec <IRQ_SubHandler_Trampoline>

4020ffe0 <UNDEF_SubHandler_Trampoline>:
4020ffe0: 803007cc eorshi r0, r0, ip, asr #15

4020ffe4 <ABORTP_SubHandler_Trampoline>:
4020ffe4: 80300810 eorshi r0, r0, r0, lsl r8

4020ffe8 <ABORTD_SubHandler_Trampoline>:
4020ffe8: 80300854 eorshi r0, r0, r4, asr r8

4020ffec <IRQ_SubHandler_Trampoline>:
4020ffec: 80300790 mlashi r0, r0, r7, r0

Thanks
  • Hi,

    What I seem to understand from your question is that you have placed your exception vectors in SRAM but the program execution jumps to addres

    0x00014010 when an interrupt occurs.

    That is quite predictable. The problem is that your Cortex-A8 core is configured as default (or due to bootloader configurations) so that the exception vectors are placed at the address 0x0014000.

    The solution, you need to program the Secure or Nonsecure Vector Base Address Coprocessor 15 Register in your Cortex A8 core like this:

    MCR p15, 0, <Rd>, c12, c0, 0

    where <Rd> corresponds to your Vector Base Address i.e. the location where you want to place your ARM exception vectors.

    For details, you can look at Cortex-A8 Technical Reference Manual. In the version of document that I have, the related documentation is in section 3.2.68 of TRM

    Regards,

    Awais Masood

    Mentor Embedded

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