Part Number: AM62D-Q1
Hi experts,
As described in the original thread, we are evaluating DDR‑MARGIN‑FW on the AM62D‑EVM.
Referring to this thread , we are skipping step 4 in readme.txt.
The device is booted using SBL NULL(AM62D FreeRTOS SDK: CCS Launch, Load and Run ), and the .out file is loaded and executed directly on the A53 core.
Q: Why is it not possible to connect to the SMS0_TIFS_0 core on HS‑FS devices?
Best regards,
O.H
