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Original question:

DRA829V: I2C Status Register (I2C_IRQSTATUS_RAW) field descriptions

DRA829V: I2C software reset and failure recovery

Jakob Bleickert
Prodigy 120 points

Part Number: DRA829V

Dear TI team,

Referring to chapter "12.1.3.4.3 I2C Software Reset" of the latest TRM (spruil1d) and register field SRST (bit 1) of the System Configuration register (I2C_SYSC), what is the scope of the reset and which registers are affected?

Is a STOP bit sent by the hardware when a transfer fails (no acknowledge received)?

Thanks a lot for your help.

Best regards,
Jakob

  • +1
    TI__Intellectual 2980 points

    Hi Jakob,

    Although, there is no explicit mention in TRM about which registers would get affected by software reset, this will reset the whole I2C state, so it means it would for sure affect the 
    I2C_IRQSTATUS_RAW, I2C_IRQSTATUS, I2C_SA (slave address), I2C_BUF, I2C_CNT, I2C_DATA, I2C_STAT etc...

    Jakob Bleickert said:
    Is a STOP bit sent by the hardware when a transfer fails (no acknowledge received)?

    No, the STOP won't be sent by hardware. The driver explicitly calls I2CMasterStop() in both interrupt and polling modes when NACK or other fatal errors occur.

    -Vinit

  • 0 in reply to Vinit Patel
    Prodigy 120 points

    Hi Vinit,

    Thank you very much.

    Best regards,
    Jakob