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DRA829J: DRA829J:About L3 cache coherency

Yuhei Shimizu
Prodigy 30 points

Part Number: DRA829J

When using MSMC-SRAM as an L3 cache, what range of cache coherency is ensured?
1.Is cache coherency ensured between the L1/L2 cache of the Cortex-A72 processor in A72SS on the MainDomain and the L1 cache of the Cortex-R5F processor in R5FSS0/1 on the MainDomain?

  • 0
    TI__Guru* 81020 points

    Hi,

    MSMC as L3 cache is a cache coherent only with coherent master.

    A72 supports a hardware coherency Its L1/L2 caches are coherent with each other and coherent with MSMC(L3 Cache) whereas, R5F is not hardware coherent, It is treated as non coherent master. 

    MSMC can be configured as either a L3 cache for A72 or SRAM.

    Best Regards,
    Sudheer