AM6442: Resistor selection for AM6442 internal PCIe Refclock

Greetings Aditya,

Where on the board are you probing? From the characteristics of this waveform it appears that you are probing somewhere in the middle of the transmission line and not towards the end of the receiver. This can potentially cause the waveform you are seeing.

Sincerely,

Lucas

Hi Lucas , 

I am Probing at R665 and R666 to capture PCIe REFCLK which is present near the PCIe connector J27 on the bottomside. Shoud we need to do any other resistor settings to get clean internal PCIe REFCLK?

Hi Lucas , 

We captured the internal PCIe Refclk in two scenarios.

1. With R346 and R333 mounted with 49.9 ohm:

2. R346 and R333 Demounted 

From the SPRACU5E document We observe a recomendation to implement 49.9 ohms parallel resistor.

We observe clock parameteres to be better in AM6442 EVK when 49.9 ohm parallel termination resistor not present . Can you let us know is this behaviour is as expected or is there anyother resistor settings to be followed.

Note: We probed the REFCLK near to the end point with PCIe switch card interfaced to AM6442 evk . We probed in via which on bottom of the endpoint.

Hello, 

Lucas is currently out of office, he will review and reply to this e2e as soon as possible following his return. 

Thanks,

Chris 

Hi Team , Attachinh the image of test environment for your refernce. I have marked the probing point in the image. The PCB board interfaced with AM6442 EVK PCIe slot is  Microchip  "EVB-PCI12000".

Hello Aditya Patil,

Can you confirm the software stack you are using -  Linux or the MCU+SDK?

Regards,

Sreenivasa

Hello Aditya Patil,

There is a likely chance that the internal terminations are enabled.

It should be OK to DNI the external 50R in case the internal pulls are enabled.

Regards,

Sreenivasa

Hi Team, we performed compliance test for AM6442 internal PCIe Reference clock with both 50-ohm termination and without 50-ohm termination and we observe jitter values exceeding the PCIe spec limits (3.1ps RMS for PCIe gen 2.0 5GT/s) in both configurations Please find the attached Jitter report for Am6442 internal PCIe Reference clock. Are the jitter values acceptable?  If not Kindly let us know for any changes to be made in AM6442 register configurations or any changes to be made in the hardware to reduce the Jitter values to adhere to PCIe specification.

Note: Test setup is same as mentioned above where "EVB-PCI12000" is interfaced with AM6442 EVK.

1. AM64_EVK_49.9ohm_Not_mounted_Report.pdf                                 

2.  AM64_EVK_49.9ohm_mounted_Report_RMS_jitter.pdf

Greetings Aditya,

I am still suspicious that the probing is not accurately showing the true quality of the signal. Just changing positions to further in the transmission line showed a better capture of the REFCLK signal without actually changing anything (even with the resistor experiments, it's still a more accurate capture). 

I see in the report that one of the probes was skew calibrated while the other was not. I also see from the picture that a differential probe (?) is being used on channel 3 of your scope, while the report lists channel 2 and 4 being single ended captures of REFCLK +/-. Were these reports taken with the setup in the picture or some other measurement setup?

Sincerely,

Lucas

Hi Lucas ,

The current measurement strategy involves probing the REFCLK transmission line at the terminal end of the trace. Specifically, the tap point is located on the bottom layer, directly beneath the ZL40264LDG1 which is surface mounted on the top layer (board thickness : ~1mm) Could you let us know if this localized probing setup sufficient to assess the Refclock jitter parameters.

Yes, report uploaded is for the measurement taken in another test setup, where 2 single ended probes are used for REFCLK + & REFCLK – as per the compliance software, the required signals for the test are automatically determined based on the selected test case. But the probing locations are same as earlier.

Justification for Skew calibration done in one probe whereas in another probe it’s not done: Actually, it was a mistake by testing team that they have used different probe in channel 4 instead of using the probe what they have used during calibration.

Hi Lucas, 

Can You confirm does our test set up (~1mm from endpoint) is good enough to measure jitter values. If not let us know how to proceed further.

Greetings Aditya,

We cannot make that confirmation for you as it's highly dependent on the particular resourcing and timelines for your project. By getting closer to the actual endpoint you've already seen there is a more accurate picture of the signal that can be obtained, but you could also experiment with different physical probes, scopes, or a compliance load board like recommended earlier. All of these different things cost time, money, or both; it is ultimately your team's responsibility to make the decision of whether or not this methodology is sufficient.

Sincerely,

Lucas

Hello Sreenivasa,

We are using Linux SDK and version 10.00.07.04, we have not added any internal pull ups or pull down. 

Could you please let us know if any termination to be added how it can be done and where actually it has to added in Linux.

Regards,

Shwetha Nayak

Hello Swetha, 

Thank you.

I am not sure i understand your query, please elaborate.

The internal terminations are enabled by default.

You might want to DNI the external terminations and measure the waveform.

Regards,

Sreenivasa

 Thank you for the clarification.

 To elaborate on our query: we wanted to understand whether the PCIe REFCLK termination on AM64x can be explicitly enabled or disabled via software (Linux SDK / device tree / registers), or if it is purely a hardware-default behavior.

 Based on your response, we understand that:

 Could you please confirm if this understanding is correct?

Hello Shwetha Nayak

Thank you.

Shwetha Nayak said:

- The REFCLK internal termination is enabled by default inside the SoC/PHY

- There is no software or Linux configuration required or available to control this

This is correct. I will check with the PCIe software expert to confirm.

Shwetha Nayak said:

- External REFCLK termination components, if present on the board, should be DNIed to avoid double termination

 Could you please confirm if this understanding is correct?

This is correct.

A termination on the end point + internal termination is supported.

There can be internal SOC + termination, SOC external termination and the END point termination -> having all the three terminations is not allowed or recommended.

Regards,

Sreenivasa

Hello Sreenivasa,

Thank you for your input.

Any further input from PCIe software expert to confirm that there is no software or Linux configuration required or available to control this?

Regards,

Shwetha

Hello Shwetha Nayak

I have not heard back, let me follow-up and update.

Regards,

Sreenivasa

Hello Shwetha Nayak

Please refer inputs i received from the expert:

the REFCLK_TERM_DIS bit in WIZ_CONFIG_SERDES_RST register is not set in Linux, so the internal termination is enabled in Linux.

Since this register bit exists, software should be able to set the bit to disable the internal termination when needed. The Linux serdes driver just doesn't implement it.

This has to be done as part of a sequence when initializing the Serdes, you cannot toggle it on or off freely.

I would recommend that you leave the internal terminations enabled and DNI external terminations when using the SOC clock as the reference clock.

Regards,

Sreenivasa

Hello Shwetha Nayak

Thank you.

Kallikuppa Sreenivasa said:

ince this register bit exists, software should be able to set the bit to disable the internal termination when needed. The Linux serdes driver just doesn't implement it.

This has to be done as part of a sequence when initializing the Serdes, you cannot toggle it on or off freely.

I suspect no.

It should be Ok to have the far end termination. Make sure the external termination is DNI.

Regards,

Sreenivasa 

Hello Shwetha Nayak

When AM64x clock is used as the Reference clock, the clock supports double termination. 

You need to understand the system implementation and handle the configuration.

The internal termination is always enabled based on the received inputs.

Please read above where the expert mentioned linux does not have implementation to configure the bit.

Regards,

Sreenivasa