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TMDS64EVM: Query regarding Hardware Flow Control Register

Sumi Mariam Mamachan
Prodigy 110 points

Part Number: TMDS64EVM
Other Parts Discussed in Thread: SYSCONFIG

Hi,

I am working with AM64x EVM using MCU+ SDK. My application runs on R5FSS0_0 core.

While debugging UART configuration, I observed two things and would like clarification.

  1. UART0 Domain Mapping

In generated ti_drivers_config.c:

#define CSL_UART0_BASE (0x2800000UL)

This corresponds to address 0x02800000.

In CCS register view I see both UARTx and MCU_UARTx instances.

Since the TRM mentions A53 and R5F cores are in the Main domain, I want to confirm:

• When building for R5FSS0_0, does CSL_UART0_BASE (0x02800000) map to UART0?
• Or is it MCU_UART0?
• How does SysConfig resolve "UART0" to a specific domain instance?

  1. EFR Register – AUTO_CTS_EN / AUTO_RTS_EN

In SysConfig, Hardware Flow Control is disabled.

However, in register view:

• UART0 and UART1 show:
AUTO_CTS_EN = 1
AUTO_RTS_EN = 1

• UART2–UART6 and MCU_UARTx instances show these bits as 0.

Even after:
- Changing UART instance in SysConfig
- Rebuilding
- Reloading the application

UART0 and UART1 still show AUTO_CTS_EN and AUTO_RTS_EN as 1.

I would like clarification on the following:

• Are these bits being set by Boot ROM or SBL before my application runs?
• Does the MCU+ SDK UART driver explicitly clear these bits when hardware flow control is disabled?
• If I require AUTO_CTS_EN and AUTO_RTS_EN to remain 0, what is the recommended approach?

Regards,

Sumi 

  • 0
    TI__Guru 56534 points

    Hi,

    Sumi Mariam Mamachan said:
    • When building for R5FSS0_0, does CSL_UART0_BASE (0x02800000) map to UART0?
    • Or is it MCU_UART0?
    • How does SysConfig resolve "UART0" to a specific domain instance?

    I believe that would be a CCS bug. In actual, the mappings are as follows:

    These mappings are correctly followed in your application as well.

    Sumi Mariam Mamachan said:
    • Are these bits being set by Boot ROM or SBL before my application runs?
    • Does the MCU+ SDK UART driver explicitly clear these bits when hardware flow control is disabled?
    • If I require AUTO_CTS_EN and AUTO_RTS_EN to remain 0, what is the recommended approach?

    I believe this is a bug. Because ROM does not sets these bits, also once set, these bits are not cleared while the UART driver is closed. 

    Hence an implementation where the AUTO CTS and RTS should be set back to 0 in the closing process of UART, in case the HW Flow Control threshold was used.

    I have filed a bug for the same. The logic of setting these bits back to 0, would probably be the API UART_lld_deInit.

    BR Vaibhav