• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 98 subscribers
  • Views 181 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TDA4VH-Q1: Clarity on CTRLMMR_WKUP_RESET_SRC_STAT values

AM62P-Q1: AM62p: Reset reason logging

cjorden
Prodigy 120 points

Part Number: AM62P-Q1
Other Parts Discussed in Thread: TDA4VH-Q1, AM62P, AM620-Q1

Hello,

I am working on a project that uses the AM62P-Q1 part, and we are trying to accurately log the reset reason for the device.

In my previous post https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1623720/tda4vh-q1-clarity-on-ctrlmmr_wkup_reset_src_stat-values

I got the details about the TDA4VH-Q1 part that we are using in a different project.

I am trying to find out if this same register is relevant for the AM62P, or if there is a different way to query the reset reason for the SoC.  I don't see that register noted in the TRM, and for the AM62p, there is no public register map spreadsheet as part of the TRM.

Also, we will be working on projects using the AM620-Q1, and would like to understand if the same method would apply to it.

 

Any guidance will be greatly appreciated.

  • 0
    Prodigy 120 points

    Upon further investigation into the J722S register sheet (which shares a lot in common with the AM62P), I was able to find the MCU_CTRL_MMR_CFG0_RST_SRC / WKUP_CTRL_MMR_CFG0_RST_SRC, which appears to be roughly analogous to the Jacinto 7's CTRL_MMR_CFG0_RESET_SRC_STAT register.  I then found those registers described in the AM62p TRM.

    In order to determine reset reason on AM62P, is WKUP_CTRL_MMR_CFG0_RST_SRC the correct register to read (from Linux on the Cortex A53 cores)?

  • +1 in reply to cjorden
    TI__Mastermind 25080 points

    Hello,

    You are correct, MCU_CTRL_MMR_CFG0_RST_SRC is the reset logging register in Sitara processors:

    The same register is mirrored in the WKUP domain:

    Regards,

    Stan