Hello,
We have been testing a design which uses a 2.0 Silicon, 1.25GHz, 4-core C667x DSP. We brought the DSP up in PCI bootmode. The input clock is 100MHz, so we set bootmode pins (12:10) to 011 per Table 2-13 of the datasheet. We measured SYSCLK out to be ~133MHz, which indicates a DSP clk rate of only 800MHz. We were expecting a clock rate of 1.25GHz (again per Table 2-13, which states that the default PLLM and PLLD values will set the DSP clock to the maximum possible rate). We read the DEVSTAT register to make sure that the bootloader settings were correct, and they were. We read the PLLM, PLLD and SECCTL registers. PLLM = 15, PLLD = 0 and OUTPUT_DIVIDE = 2, which gives us an 800MHz clock, not a 1.25GHz clock. We played around with different bootmode PLL settings, and in each case the default PLLM and PLLD values written by the Boot ROM provide an 800MHz clock for the given input clock. Is this intentional?
Thanks.
-Courtney
