Part Number: DRA829J-Q1
Other Parts Discussed in Thread: BEAGLEY-AI, DRA829, SK-TDA4VM
While testing the MMCSD1 interface in SDR104 mode on a custom board using a DRA829 SoC, I noticed an issue with some SDcards vendors but this issue affect other evaluation boards like the SK-TDA4VM (J721e), Beagley-AI (J722s) but not the BBAI64 (J721e). (Issue reproduced with SD DDR50 before removing SDR104 limitation.)
Expected result:[ 3.119790] mmc1: new ultra high speed SDR104 SDXC card at address 5048[ 3.126756] mmcblk1: mmc1:5048 SD64G 58.0 GiB
Result with a cheap (fake?) SDcard:[ 3.142101] mmc1: new high speed SDXC card at address b369[ 3.147949] mmcblk1: mmc1:b369 SDABC 58.2 GiB
I also noticed a boot issue with u-boot or the Linux kernel were with some of theses (not all) dubious SDcards:
mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bitWaiting for root device /dev/mmcblk1p2...mmc1: error -110 whilst initialising SD card
It tourn out that the BBAI64 (j721e) was upstreamed with the MMCSD1 interface limited to SD High Speed only in u-boot[1].
It seems that the BeagleBoard AI64 reused some devicetree examples from other TI K3 SoC.
Indeed, first K3 SoC (AM65xx) seems to have had SD UHS issues in the past and so the SD UHS support was completely disabled:
"arm: dts: k3-am625-sk-u-boot: Disable UHS speed modes on MMCSD1 instance
Instabilities were observed on few SD cards when UHS speed modes were enabled. Therefore, disable UHS modes by adding the sdhci-cap-masks, in sdhci1 device tree node." [2]
"arm: dts: k3-am654-base-board: Limit Sd card to High speed modes
There's an issue with the base board in which the power cycle circuit takes way longer to power down than expected by mmc core. code. This prevents the card from enumerating in UHS modes.
Disable UHS modes for this board until a new board revision fixes the issue." [3]
"arm64: dts: k3: Add u-boot specific nodes
arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+&sdhci1 {
- u-boot,dm-spl;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- sdhci-caps-mask = <0x7 0x0>; +};
" [4]
So, this SDcard issue can be reproduced when u-boot configure the MMCSD interface in UHS mode, the kernel seems to have some issue when it verify the voltage switch signal with some SDcards.
The mmc driver core function mmc_sd_setup_card() [5] retrieve the sd card infos using mmc_read_switch() [6]. The 'sd3_bus_mode' value contains the flags describing what the SD cards really support.
But for some reason with some SDcard, only SD HS mode is advertised:
card->sw_caps.sd3_bus_mode = 3
While with other SDcard, all UHS mode are advertised:
card->sw_caps.sd3_bus_mode 31
sd3_bus_mode value is set by mmc_sd_switch() [7] function that send the SD_SWITCH opcode:
mmc_sd_switch(.... &status);
...
card->sw_caps.sd3_bus_mode = status[13];
Disabling SD UHS mode allows to keep the SDcard powered by a 3,3V VDD_SD_DV powersupply.
With SD UHS mode enabled by u-boot, VDD_SD_DV is set to 1,8V. When the kernel boot, with some SD cards (SanDisk one) the PMIC driver receive an IRQ about a LDO1 voltage outside of its expected range:
[ 3.149028] tps6594 0-004c: Error IRQ trap overvoltage for LDO1
(Issue reproduced on SK-TDA4VM)
So, we disabled SD UHS in uboot in order to let the Linux kernel configure SD UHS properly.
Note:
For the AM57xx SoC, the TI-SDK provide a short list of "Functional" SDcards [8].
Is this list still apply for newer K3 SoC? Even if the MMCSD controller is not the same.
About the MMCSD SDR104 support for DRA829 SoC:
SD UHS SDR104 has been disabled for all J721e SoC by commit [9] due to errata i2090.
But this errata only apply for J721e SR1.0 [10]
i2090 — MMCSD: MMCSD1 and MMCSD2 Speed Issue
SILICON REVISIONS AFFECTED
SR 1.0 | SR 1.1 | SR 2.0
YES | NO | NO
The TI J721e EVM board (REV A) and other J721e based boards (BeagleboneAI64 and SK-TDA4VM) publicly available are using a SoC SR1.1.
The J721e SR1.0 was used on early J721E EVM prototype board rev E8 [11], the J721e EVM rev E8A prototype already use a SR1.1.
While at it, the j721e-main devicetree needs to be updated with the delay values for legacy and high speed modes, based on the latest revised datasheet SPRSP36K released in April 2024 [12].
(MMC1/2 - SD/SDIO Interface): Updated/Changed the
"OTAPDLYENA, DELAY ENABLE" and "OTAPDLYSEL, DELAY VALUE" for the
Default Speed and High Speed modes from "0x0" to "0x1"
Table 6-86. MMC1/2 DLL Delay Mapping for All Timing Modes
(SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024)
A patch was sent on the kernel mailing list [13].
[1] https://source.denx.de/u-boot/u-boot/-/commit/7f78636667f4dcab784548651a2cc3abd60476cf#line_8b6ae81ae_A139
[2] beagleboard/u-boot@5c309ad
[3] https://source.denx.de/u-boot/u-boot/-/commit/9aa4302c02de12517bf08d0fc487bf4da290c3e2
[4] https://source.denx.de/u-boot/u-boot/-/commit/853f7f5018d9b67b6039a78127c44e2daa467204
[5] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/mmc/core/sd.c?h=linux-6.1.y#n944
[6] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/mmc/core/sd.c?h=linux-6.1.y#n324
[7] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/mmc/core/sd_ops.c?h=linux-6.1.y#n310
[8] https://software-dl.ti.com/processor-sdk-linux/esd/AM57X/11_01_02_01/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Storage/MMC-SD.html#supported-ultra-high-speed-uhs-modes
[9] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=eb8f6194e8074d7b00642dd75cf04d13e1b218e4
[10] www.ti.com/.../sprz455.pdf
[11] www.ti.com/.../SPRR411
[12] www.ti.com/.../tda4vm.pdf
[13] https://lore.kernel.org/linux-omap/20260218203823.1825554-1-romain.naour@smile.fr/
