The alg can run dm3730，but now i migrate it to the dm8148 ,it can not run .
CE_DEBUG=2 LOG:
m:~/1# CE_DEBUG=2 ./app_remote.xv5T -s xe674
205906.75>[t=0x000003e3] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+E] Global_init> Enter
205906.75>[t=0x00000516] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] Global_init> This program was built with the following packages:
205906.76>[t=0x00000579] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package gnu.targets (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdctools_3_22_04_46/packages/gnu/targets/) [1, 0, 1]
205906.79>[t=0x0000060a] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package gnu.targets.arm (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdctools_3_22_04_46/packages/gnu/targets/arm/) [1, 0, 0, 0]
205906.81>[t=0x0000069e] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package gnu.targets.arm.rtsv5T (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdctools_3_22_04_46/packages/gnu/targets/arm/rtsv5T/) [1, 0, 0, 0]
205906.82>[t=0x0000073a] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.utils.loggers (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/osal_1_21_01_08/packages/ti/sdo/utils/loggers/) [1, 0, 0]
205906.85>[t=0x000007cf] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.xdcruntime.linux (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/osal_1_21_01_08/packages/ti/sdo/xdcruntime/linux/) [1, 0, 0]
205906.87>[t=0x00000868] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.ce.global (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/codec_engine_3_21_01_23/packages/ti/sdo/ce/global/) [1, 0, 0]
205906.89>[t=0x000008fd] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.syslink (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/syslink_2_00_04_83/packages/ti/syslink/) [1, 0, 0, 0]
205906.90>[t=0x0000098a] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.linuxutils.cmem (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/linuxutils_3_21_00_04/packages/ti/sdo/linuxutils/cmem/) [2, 2, 0]
205906.92>[t=0x00000a25] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.xdais.dm (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdais_7_21_01_07/packages/ti/xdais/dm/) [1, 0, 7]
205906.95>[t=0x00000ac3] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.ce.utils.xdm (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/codec_engine_3_21_01_23/packages/ti/sdo/ce/utils/xdm/) [1, 0, 2]
205906.96>[t=0x00000b5d] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.xdais (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdais_7_21_01_07/packages/ti/xdais/) [1, 2.0, 1]
205906.98>[t=0x00000be6] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.ce.node (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/codec_engine_3_21_01_23/packages/ti/sdo/ce/node/) [1, 0, 0]
205907.00>[t=0x00000c79] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.fc.global (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/framework_components_3_21_02_32/packages/ti/sdo/fc/global/) [1, 0, 0]
205907.03>[t=0x00000d13] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.catalog.arm.cortexa8 (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdctools_3_22_04_46/packages/ti/catalog/arm/cortexa8/) [1, 0, 0]
205907.04>[t=0x00000dae] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.catalog.peripherals.hdvicp2 (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdctools_3_22_04_46/packages/ti/catalog/peripherals/hdvicp2/) []
205907.06>[t=0x00000e4d] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.catalog (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdctools_3_22_04_46/packages/ti/catalog/) [1, 0, 0]
205907.07>[t=0x00000ed9] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.catalog.c6000 (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdctools_3_22_04_46/packages/ti/catalog/c6000/) [1, 0, 0, 0]
205907.10>[t=0x00000f6d] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.catalog.arm.peripherals.timers (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdctools_3_22_04_46/packages/ti/catalog/arm/peripherals/timers/) []
205907.12>[t=0x00053391] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.catalog.arm.cortexm3 (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdctools_3_22_04_46/packages/ti/catalog/arm/cortexm3/) [1, 0, 0]
205907.14>[t=0x00053434] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.platforms.evmTI814X (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/xdctools_3_22_04_46/packages/ti/platforms/evmTI814X/) [1, 0, 0]
205907.15>[t=0x000534d0] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.ce.osal (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/codec_engine_3_21_01_23/packages/ti/sdo/ce/osal/) [2, 0, 2]
205907.18>[t=0x00053562] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.ce.ipc.dsplink (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/codec_engine_3_21_01_23/packages/ti/sdo/ce/ipc/dsplink/) [2, 0, 1]
205907.20>[t=0x000535fe] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.ce.osal.linux (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/codec_engine_3_21_01_23/packages/ti/sdo/ce/osal/linux/) [2, 0, 1]
205907.21>[t=0x00053698] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.ce.ipc (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/codec_engine_3_21_01_23/packages/ti/sdo/ce/ipc/) [2, 0, 1]
205907.23>[t=0x00053729] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.ce.alg (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/codec_engine_3_21_01_23/packages/ti/sdo/ce/alg/) [1, 0, 1]
205907.26>[t=0x000537bb] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.ce (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/codec_engine_3_21_01_23/packages/ti/sdo/ce/) [1, 0, 6]
205907.28>[t=0x00053847] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package ti.sdo.ce.universal (/mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/codec_engine_3_21_01_23/packages/ti/sdo/ce/universal/) [1, 0, 0]
205907.29>[t=0x000538e0] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+4] package app.sol1.cmd (/mnt/work/proj/app/sol1/cmd/) [1, 0, 0]
205907.29>[t=0x00053a13] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+E] Global_atexit> Enter (fxn=0x2e8a0)
205907.31>[t=0x00053ac0] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+E] Global_atexit> Enter (fxn=0x33d10)
205907.31>[t=0x00053b7d] [tid=0x400b7000] ti.sdo.ce.ipc.Processor: [+2] Processor_init> SysLink_setup()...
205907.32>[t=0x00058360] [tid=0x400b7000] ti.sdo.ce.ipc.Processor: [+2] Processor_init> ... SysLink_setup() done
205907.32>[t=0x000584e2] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+E] Global_atexit> Enter (fxn=0x2f464)
205907.34>[t=0x00058583] [tid=0x400b7000] ti.sdo.ce.alg: [+E] ALG_init> Enter
205907.34>[t=0x000585c8] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[0] = 0x0
205907.35>[t=0x00058605] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[1] = 0x0
205907.35>[t=0x00058640] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[2] = 0x0
205907.35>[t=0x00058712] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[3] = 0x0
205907.37>[t=0x0005874f] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[4] = 0x0
205907.37>[t=0x0005878a] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[5] = 0x0
205907.39>[t=0x000587c5] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[6] = 0x0
205907.39>[t=0x00058800] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[7] = 0x0
205907.39>[t=0x0005883b] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[8] = 0x0
205907.40>[t=0x00058875] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[9] = 0x0
205907.40>[t=0x000588b0] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[10] = 0x0
205907.42>[t=0x000588eb] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[11] = 0x0
205907.42>[t=0x00058927] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[12] = 0x0
205907.42>[t=0x00058964] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[13] = 0x0
205907.43>[t=0x0005899f] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[14] = 0x0
205907.43>[t=0x000589db] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[15] = 0x0
205907.45>[t=0x00058a16] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[16] = 0x0
205907.45>[t=0x00058a52] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[17] = 0x0
205907.45>[t=0x00058a8e] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[18] = 0x0
205907.46>[t=0x000aa9bd] [tid=0x400b7000] ti.sdo.ce.alg: [+E] _ALG_sems[19] = 0x0
205907.46>[t=0x000aaa00] [tid=0x400b7000] ti.sdo.ce.alg: [+X] ALG_init> Exit
205907.48>[t=0x000aaa39] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+E] Global_atexit> Enter (fxn=0x27aa8)
205907.50>[t=0x000aaac8] [tid=0x400b7000] ti.sdo.ce.Engine: [+6] Engine_init> CE debugging on (CE_DEBUG=2; allowed CE_DEBUG levels: 1=min, 2=good, 3=max)
205907.50>[t=0x000aab3a] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+E] Global_atexit> Enter (fxn=0x1f218)
205907.51>[t=0x000aabb7] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] Engine addEngineToList(0xa0ea0, 1)
205907.51>[t=0x000aac05] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+E] Memory_alloc> Enter(0x34)
205907.53>[t=0x000aac5b] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+X] Memory_alloc> return (0xcf620)
205907.53>[t=0x000aacac] [tid=0x400b7000] ti.sdo.ce.Engine: Engine addEngineToList> Adding desc: name = local, remoteName = (null)
205907.54>[t=0x000aad10] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+E] Memory_alloc> Enter(0x30)
205907.54>[t=0x000aad58] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+X] Memory_alloc> return (0xcf658)
205907.56>[t=0x000aae18] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+E] Global_atexit> Enter (fxn=0x2ae6c)
205907.56>[t=0x000aae8d] [tid=0x400b7000] ti.sdo.ce.Server: [+E] Server_init()
205907.57>[t=0x000aaecf] [tid=0x400b7000] ti.sdo.ce.Server: [+E] Server_init> Global_useLinkArbiter = 0
205907.57>[t=0x000aaf30] [tid=0x400b7000] ti.sdo.ce.osal.Global: [+E] Global_atexit> Enter (fxn=0x25fd4)
205907.59>[t=0x000aaf9f] [tid=0x400b7000] xdc.runtime.Main: main> apps.sol1.cmd.darklight
205907.59>[t=0x000aaff4] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] Engine_addStubFxns('UNIVERSAL_STUBS', 0xa0fa4)
205907.60>[t=0x000ab053] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] Engine_addStubFxns> return (0)
205907.60>[t=0x000ab0b8] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] Engine_add(0xbeadbb94)
205907.62>[t=0x000ab110] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] Engine addEngineToList(0xbeadbb94, 0)
205907.64>[t=0x000ab16a] [tid=0x400b7000] ti.sdo.ce.Engine: Engine addEngineToList> Adding desc: name = darklight, remoteName = all_DSP.xe674
205907.64>[t=0x000ab1d2] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] Engine_add> return (0)
205907.64>
205907.64>---smain---engineName--- is:darklight
205907.64>
205907.64>smain---begin
205907.64>
205907.65>smain---Memory_alloc---inBuf
205907.65>[t=0x000ab30d] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+4] Memory_contigAlloc> CMEM_alloc(0xa8c00) = 0x40ba1000.
205907.67>[t=0x000ab375] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+4] Memory_contigAlloc> CMEM_getPhys(0x40ba1000) = 0xa0755000.
205907.67>
205907.67>inBuf---addr---is:0x40ba1000
205907.67>
205907.67>smain---Memory_alloc---outBuf
205907.68>[t=0x000ab45c] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+4] Memory_contigAlloc> CMEM_alloc(0xa8c00) = 0x40d34000.
205907.70>[t=0x000ab4d8] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+4] Memory_contigAlloc> CMEM_getPhys(0x40d34000) = 0xa06ac000.
205907.70>
205907.70>outBuf---addr---is:0x40d34000
205907.70>
205907.70>smain---Memory_alloc---imageBuf
205907.71>[t=0x000ab5ca] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+4] Memory_contigAlloc> CMEM_alloc(0xfd200) = 0x40e0f000.
205907.71>[t=0x000ab62e] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+4] Memory_contigAlloc> CMEM_getPhys(0x40e0f000) = 0xa05ae000.
205907.71>
205907.71>imageBuf---addr---is:0x40e0f000
205907.71>
205907.73>smain---Memory_alloc---tableBuf
205907.73>[t=0x000ab6d1] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+4] Memory_contigAlloc> CMEM_alloc(0x7fc) = 0x40f1b000.
205907.75>[t=0x000ab734] [tid=0x400b7000] ti.sdo.ce.osal.Memory: [+4] Memory_contigAlloc> CMEM_getPhys(0x40f1b000) = 0xa07ff000.
205907.75>
205907.75>tableBuf---addr---is:0x40f1b000
205907.75>
205907.75>memcpy---tableBuf
205907.75>
205907.75>smain---Engine_open
205907.76>[t=0x000ab84a] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] Engine_open> Enter('darklight', 0xbeadbb54, 0xbeadbaf4)
205907.78>[t=0x000ab8ac] [tid=0x400b7000] ti.sdo.ce.Engine: [+1] Engine_open> desc->memMap [0x0], desc->useExtLoader [0]
205907.78>[t=0x000ab907] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] rmsInit> Enter(engine=0xcf788, ec=0xbeadbaf4)
205907.79>[t=0x000ab958] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] rmsInit> engine->desc = 0xcf6d0
205907.79>[t=0x000ab99d] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] rmsInit> engine->desc->algTab = 0x0
205907.81>[t=0x000fd7cc] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] rmsInit> engine has server!
205907.81>[t=0x000fd814] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] rmsInit> engine->procId = DSP
205907.82>[t=0x000fd860] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] rmsInit> engine->coreId = 0
205907.82>[t=0x000fd8a9] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] rserverOpen('all_DSP.xe674'), count = 0
205907.84>[t=0x000fd8f4] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] rserverOpen >, memMap = 0x0, useExtLoader = 0
205907.85>[t=0x000fd952] [tid=0x400b7000] ti.sdo.ce.ipc.Processor: [+E] Processor_create> Enter(imageName='all_DSP.xe674', memMap='(null)', attrs=0xbeadbad4)
205907.85>[t=0x000fda09] [tid=0x400b7000] ti.sdo.ce.ipc.Processor: [+E] doCmd> Enter (cmdId=1, proc=0xcf7d0)
205907.87>[t=0x000fda81] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+X] getCmd_d> Exit (result=1)
205907.87>[t=0x000fdacd] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+E] Processor_create_d> Enter(proc=0xcf7d0)
205907.89>[t=0x000fdb1d] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> Retrieving CPU ID for 'DSP'...
205907.90>[t=0x000fdb75] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> Opening DSP ProcMgr for cpuId 0...
205907.90>[t=0x000fdc18] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> Attaching to DSP...
205907.92>[t=0x000ff5c7] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> Loading all_DSP.xe674 on DSP (1 args)...
205907.93>[t=0x00110ba1] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> calling Ipc_control(LOADCALLBACK)...
205907.93>[t=0x0011ecbc] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> Ipc_control(LOADCALLBACK) status: 0
205907.95>[t=0x0011ed39] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> Starting DSP ...
205907.95>[t=0x001212d2] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> Ipc_control(STARTCALLBACK) status: 159195136
205907.96>[t=0x0012136d] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> calling HeapBufMP_create(): nblocks 64, blocksize 0x1000
205907.98>[t=0x0012221d] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> MessageQ_registerHeap(heapH: 0xcfec8, heapId: 0)
205908.00>[t=0x001222db] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+1] Processor_create_d> CMEM block #0 found, doing ProcMgr_map(0xa0000000, 0x800000)...
205908.00>[t=0x0012237f] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+2] Processor_create_d> return (1)
205908.01>[t=0x001223f2] [tid=0x400b7000] ti.sdo.ce.ipc.Processor: [+X] doCmd> Exit (result=1)
205908.01>[t=0x0012243e] [tid=0x400b7000] ti.sdo.ce.ipc.Processor: [+X] Processor_create> return (0xcf7d0)
205908.03>[t=0x0012248d] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] rserverOpen('all_DSP.xe674'): 0xcf658 done.
205908.03>[t=0x0012288c] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+E] getCmd_d> Enter (proc=0x40af8dc4)
205908.04>[t=0x00122be2] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] checkServer(0xcf788)
205908.06>[t=0x00122d2c] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] rmsInit> RMS initialized(0xcf788); CE_DEBUG on, setting DSP trace mask to ti.sdo.ce.%+EX1234567;ti.sdo.fc.%+EX12345678;ti.sdo.ce.rms=67;ti.sdo.fc.dman3-2;ti.sdo.fc.dskt2-2;time=2
205908.07>[t=0x00122df5] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] Engine_setTrace> Enter(engine=0xcf788, mask='ti.sdo.ce.%+EX1234567;ti.sdo.fc.%+EX12345678;ti.sdo.ce.rms=67;ti.sdo.fc.dman3-2;ti.sdo.fc.dskt2-2;time=2')
205908.09>[t=0x00122ef8] [tid=0x400b7000] ti.sdo.ce.Engine: [+1] Engine_setTrace> Requesting DSP set trace ...
205908.09>[t=0x0012300f] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] Engine_setTrace> return(0)
205908.10>[t=0x00123138] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] Engine_fwriteTrace> returning count [0]
205908.10>[t=0x0012319e] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] Engine_initFromServer(0xcf788)
205908.12>[t=0x001231ed] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] Engine_getNumServerAlgs(0xcf788 0xbeadba40)
205908.14>[t=0x001232d2] [tid=0x400b7000] ti.sdo.ce.Engine: [+2] Engine_getNumServerAlgs> number of server algs = 1
205908.14>[t=0x00123341] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] Engine_getNumServerAlgs> Returning 0
205908.15>[t=0x0012338d] [tid=0x400b7000] ti.sdo.ce.Engine: [+2] Engine_initFromServer> Number of remote algs statically configured in engine: 0
205908.17>[t=0x001233f0] [tid=0x400b7000] ti.sdo.ce.Engine: [+2] Engine_initFromServer> Allocating descriptor array for [1] server algs
205908.17>[t=0x00123456] [tid=0x400b7000] ti.sdo.ce.Engine: [+2] Engine_initFromServer> Initializing descriptor array for [1] server algs
205908.18>[t=0x001234b8] [tid=0x400b7000] ti.sdo.ce.Engine: [+2] Engine_initFromServer> Sending RMS_GETALG command for alg [0]
205908.20>[t=0x001235c0] [tid=0x400b7000] ti.sdo.ce.Engine: [+1] Engine_initFromServer engine->server = 0xcf658
205908.20>
205908.20>[t=0x0012361f] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] Engine_initFromServer> Returning 0
205908.21>[t=0x00123668] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] Engine_open> return(0x$x)
205908.21>
205908.21>---UNIVERSAL_create---
205908.23>[t=0x001236e3] [tid=0x400b7000] ti.sdo.ce.universal.UNIVERSAL: [+E] UNIVERSAL_create> Enter (engine=0xcf788, name='darklight', params=0x0 (size=0x0))
205908.23>[t=0x00123762] [tid=0x400b7000] ti.sdo.ce.VISA: [+E] VISA_create(0xcf788, 'darklight', 0x0, 0x648, 'ti.sdo.ce.universal.IUNIVERSAL')
205908.25>[t=0x001237d3] [tid=0x400b7000] ti.sdo.ce.VISA: [+E] VISA_create2(0xcf788, 'darklight', 0x0, 0x0, 0x648, 'ti.sdo.ce.universal.IUNIVERSAL')
205908.26>[t=0x001238cb] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] Engine_createNode(0xcf788, 'darklight', 648, 0x0, 0x0, 0xbeadba50)
205908.26>[t=0x00123935] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] Engine> allocNode Enter(engine=0xcf788, impId='darklight')
205908.28>[t=0x00123991] [tid=0x400b7000] ti.sdo.ce.Engine: [+E] Engine> allocNode(). Calling Comm_create(NULL, NULL)
205908.29>[t=0x00124984] [tid=0x400b7000] ti.sdo.ce.Engine: [+6] Engine_createNode> Remote node creation FAILED (0x80008008).
205908.29>[t=0x00124ac4] [tid=0x400b7000] ti.sdo.ce.Engine: [+X] Engine_fwriteTrace> returning count [0]
205908.31>[t=0x00176c5a] [tid=0x400b7000] ti.sdo.ce.Engine: [+2] Engine_createNode> Returning 0x0
205908.31>[t=0x00176cc0] [tid=0x400b7000] ti.sdo.ce.VISA: [+2] VISA_create2> FAILED to create remote codec (0x8).
205908.32>[t=0x00176d1b] [tid=0x400b7000] ti.sdo.ce.VISA: [+E] VISA_delete(0xcffc8)
205908.32>[t=0x00176d5b] [tid=0x400b7000] ti.sdo.ce.VISA: [+5] VISA_delete> deleting codec (localQueue=0x0, remoteQueue=0xffff)
205908.34>[t=0x00176deb] [tid=0x400b7000] ti.sdo.ce.universal.UNIVERSAL: [+X] UNIVERSAL_create> return (0x0)
205908.35>[t=0x00176e42] [tid=0x400b7000] ti.sdo.ce.universal.UNIVERSAL: [+E] UNIVERSAL_delete> Enter (handle=0x0)
205908.35>[t=0x00176e93] [tid=0x400b7000] ti.sdo.ce.VISA: [+E] VISA_delete(0x0)
205908.37>[t=0x00176ece] [tid=0x400b7000] ti.sdo.ce.universal.UNIVERSAL: [+X] UNIVERSAL_delete> return
205908.37>[t=0x00176f3e] [tid=0x400b7000] ti.sdo.ce.Engine: Engine cleanup()> Num engines = 2, removing engine local
205908.39>[t=0x00176f99] [tid=0x400b7000] ti.sdo.ce.Engine: Engine cleanup()> Num engines = 1, removing engine darklight
205908.39>[t=0x0017701f] [tid=0x400b7000] ti.sdo.ce.ipc.Processor: [+E] doCmd> Enter (cmdId=3, proc=0x0)
205908.40>[t=0x00177084] [tid=0x40af9490] ti.sdo.ce.ipc.Processor: [+X] getCmd_d> Exit (result=3)
205908.40>[t=0x0017719a] [tid=0x400b7000] ti.sdo.ce.ipc.Processor: [+X] doCmd> Exit (result=1)
205908.42>[t=0x0017721d] [tid=0x400b7000] ti.sdo.ce.ipc.Processor: [+2] Processor cleanup()> SysLink_destroy()...
205908.43>Assertion at Line no: 343 in /mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/syslink_2_00_04_83/packages/ti/syslink/procMgr/hlos/usr/ProcMgr.c: (ProcMgr_state.procHandles [i] == NULL) : failed
205908.45>Assertion at Line no: 2144 in /mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/syslink_2_00_04_83/packages/ti/syslink/procMgr/hlos/usr/ProcMgr.c: (handle != NULL) : failed
205908.46>Assertion at Line no: 2144 in /mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/syslink_2_00_04_83/packages/ti/syslink/procMgr/hlos/usr/ProcMgr.c: (handle != NULL) : failed
205908.48>Assertion at Line no: 2144 in /mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/syslink_2_00_04_83/packages/ti/syslink/procMgr/hlos/usr/ProcMgr.c: (handle != NULL) : failed
205908.50>Assertion at Line no: 2144 in /mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/syslink_2_00_04_83/packages/ti/syslink/procMgr/hlos/usr/ProcMgr.c: (handle != NULL) : failed
205908.51>Assertion at Line no: 2144 in /mnt/hd-8148-dvsdk/ti-ezsdk_dm814x-evm_5_03_00_09/component-sources/syslink_2_00_04_83/packages/ti/syslink/procMgr/hlos/usr/ProcMgr.c: (handle != NULL) : failed
205908.53>[t=0x00177d6b] [tid=0x400b7000] ti.sdo.ce.ipc.Processor: [+2] Processor cleanup()> ... SysLink_destroy() complete
205908.53>root@dm814x-evm:~/1#
the dm8148 server.cfg:
/*
* ======== server.cfg ========
*
* For details about the packages and configuration parameters used throughout
* this config script, see the Codec Engine Configuration Guide (link
* provided in the release notes) and the Codec Engine Package Documentation at:
* http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ce/latest_2_x/xdoc/index.html
* which references to Framework Components configurable modules under ti.sdo.fc.
*/
/* scratch groups */
var MAXGROUPS = 20;
var GROUP_2 = 2;
$trace("platformName = '" + Program.platformName + "'", 1, ['genserver']);
function createHeapMem(size, sectionName, heapName) {
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams = new HeapMem.Params();
heapMemParams.size = size;
heapMemParams.sectionName = sectionName;
Program.sectMap[sectionName] = heapName;
return HeapMem.create(heapMemParams);
}
/* heap config */
var internalMemoryName = 'IRAM';
var internalHeapSize = 0xc000; // 48 kB
var externalMemoryName = 'DDR3';
var externalHeapSize = 0x20000; // 128 kB
/* Configure internal and external heaps */
Program.global.EXT_HEAP =
createHeapMem(externalHeapSize, ".EXT_HEAP", externalMemoryName);
Program.global.INT_HEAP =
createHeapMem(internalHeapSize, ".INT_HEAP", internalMemoryName);
var DDRALGMemoryName = "DDRALGHEAP";
var DDRALGHeapSize = Program.platform.externalMemoryMap[DDRALGMemoryName].len;
Program.global.EXTALG_HEAP = createHeapMem(DDRALGHeapSize, ".EXTALG_HEAP", DDRALGMemoryName);
/* Place code */
Program.sectMap[".text"] = externalMemoryName;
var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
Timer.intFreq.hi = 0;
Timer.intFreq.lo = 20000000;
/* Set the default heap to the external heap */
var Memory = xdc.useModule('xdc.runtime.Memory');
Memory.defaultHeapInstance = Program.global.EXT_HEAP;
/* end heap config */
/* Setup xdcruntime proxys */
xdc.useModule('ti.sysbios.xdcruntime.Settings');
/*
* Configure CE's OSAL. This codec server only builds for the BIOS-side of
* a heterogeneous system, so use the "DSPLINK_BIOS" configuration.
*/
var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global');
osalGlobal.runtimeEnv = osalGlobal.DSPLINK_BIOS;
/* IPC-related config */
xdc.useModule('ti.sdo.ce.ipc.dsplink.dsp.Settings');
var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
var settings = xdc.useModule('ti.sdo.ipc.family.Settings');
var procNames = settings.getDeviceProcNames();
MultiProc.setConfig("DSP", procNames);
var SharedRegion_map = {};
SharedRegion_map["SysLink: HOST<--->DSP"] = 0;
SharedRegion_map["Ipc"] = 1;
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
var syslinkSharedMem = Program.cpu.memoryMap["DDR3_SR0"];
var ipcSharedMem = Program.cpu.memoryMap["DDR3_SR1"];
var entry = new SharedRegion.Entry();
entry.base = syslinkSharedMem.base;
entry.len = syslinkSharedMem.len;
entry.ownerProcId = MultiProc.getIdMeta("HOST");
entry.isValid = true;
entry.name = "SYSLINK";
SharedRegion.setEntryMeta(
SharedRegion_map["SysLink: HOST<--->DSP"], /* index */
entry
);
var entry2 = new SharedRegion.Entry();
entry2.base = ipcSharedMem.base;
entry2.len = ipcSharedMem.len;
entry2.ownerProcId = MultiProc.getIdMeta("HOST");
entry2.isValid = true;
entry2.createHeap = true;
entry2.cacheEnable = true;
entry2.name = "SR1";
SharedRegion.setEntryMeta(
SharedRegion_map["Ipc"], /* index */
entry2
);
/*
* ======== Server Configuration ========
*/
var Server = xdc.useModule('ti.sdo.ce.Server');
/* The server's stackSize. More than we need... but safe. */
Server.threadAttrs.stackSize = 16384;
/* The servers execution priority */
Server.threadAttrs.priority = Server.MINPRI;
/*
* The optional stack pad to add to non-configured stacks. This is well
* beyond most codec needs, but follows the approach of "start big and
* safe, then optimize when things are working."
*/
Server.stackSizePad = 9000;
/*
* "Use" the various codec modules; i.e., implementation of codecs.
* All these "xdc.useModule" commands provide a handle to the codecs,
* which we'll use to initialize config params and add the codecs to
* the Server.algs array.
*/
var DARKLIGHT = xdc.useModule('adas.darklight.DARKLIGHT');
DARKLIGHT.serverFxns = "UNIVERSAL_SKEL";
DARKLIGHT.stubFxns = "UNIVERSAL_STUBS";
DARKLIGHT.manageInBufsCache = [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true];
DARKLIGHT.manageInOutBufsCache = [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true];
DARKLIGHT.manageOutBufsCache = [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true];
/*
* The array of algorithms this server can serve up. This array also
* configures details about the threads which will be created to run the
* algorithms (e.g. stack sizes, priorities, etc.).
*/
Server.algs = [
{name: "darklight", mod: DARKLIGHT , threadAttrs: {
stackMemId: 0, priority: Server.MINPRI + 1},
groupId : 2,
},
];
/* to link in debug/trace FC libs, uncomment one of these */
// xdc.useModule('ti.sdo.fc.global.Settings').profile = "debug");
// xdc.useModule('ti.sdo.fc.global.Settings').profile = "debug_trace");
// xdc.useModule('ti.sdo.fc.global.Settings').profile = "trace");
/*
* ======== DSKT2 (XDAIS Alg. memory allocation) configuration ========
*
* DSKT2 is the memory manager for all algorithms running in the system,
* granting them persistent and temporary ("scratch") internal and external
* memory. We configure it here to define its memory allocation policy.
*
* DSKT2 settings are critical for algorithm performance.
*
* First we assign various types of algorithm internal memory (DARAM0..2,
* SARAM0..2,IPROG, which are all the same on a C64+ DSP) to "L1DHEAP"
* defined in the .tcf file as an internal memory heap. (For instance, if
* an algorithm asks for 5K of DARAM1 memory, DSKT2 will allocate 5K from
* L1DHEAP, if available, and give it to the algorithm; if the 5K is not
* available in the L1DHEAP, that algorithm's creation will fail.)
*
* The remaining segments we point to the "DDRALGHEAP" external memory segment
* (also defined in the.tcf) except for DSKT2_HEAP which stores DSKT2's
* internal dynamically allocated objects, which must be preserved even if
* no codec instances are running, so we place them in "DDR2" memory segment
* with the rest of system code and static data.
*/
var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');
DSKT2.DARAM0 = "INT_HEAP";
DSKT2.DARAM1 = "INT_HEAP";
DSKT2.DARAM2 = "INT_HEAP";
DSKT2.SARAM0 = "INT_HEAP";
DSKT2.SARAM1 = "INT_HEAP";
DSKT2.SARAM2 = "INT_HEAP";
DSKT2.ESDATA = "EXTALG_HEAP";
DSKT2.IPROG = "INT_HEAP";
DSKT2.EPROG = "EXTALG_HEAP"
DSKT2.DSKT2_HEAP = "EXT_HEAP";
/*
* Next we define how to fulfill algorithms' requests for fast ("scratch")
* internal memory allocation; "scratch" is an area an algorithm writes to
* while it processes a frame of data and is discarded afterwards.
*
* First we turn off the switch that allows the DSKT2 algorithm memory manager
* to give to an algorithm external memory for scratch if the system has run
* out of internal memory. In that case, if an algorithm fails to get its
* requested scratch memory, it will fail at creation rather than proceed to
* run at poor performance. (If your algorithms fail to create, you may try
* changing this value to "true" just to get it running and optimize other
* scratch settings later.)
*
* Setting "algorithm scratch sizes", is a scheme we use to minimize internal
* memory resources for algorithms' scratch memory allocation. Algorithms that
* belong to the same "scratch group ID" -- field "groupId" in the algorithm's
* Server.algs entry above, reflecting the priority of the task running the
* algorithm -- don't run at the same time and thus can share the same
* scratch area. When creating the first algorithm in a given "scratch group"
* (between 0 and 19), a shared scratch area for that groupId is created with
* a size equal to SARAM_SCRATCH_SIZES[<alg's groupId>] below -- unless the
* algorithm requests more than that number, in which case the size will be
* what the algorithm asks for. So SARAM_SCRATCH_SIZES[<alg's groupId>] size is
* more of a groupId size guideline -- if the algorithm needs more it will get
* it, but getting these size guidelines right is important for optimal use of
* internal memory. The reason for this is that if an algorithm comes along
* that needs more scratch memory than its groupId scratch area's size, it
* will get that memory allocated separately, without sharing.
*
* This DSKT2.SARAM_SCRATCH_SIZES[<groupId>] does not mean it is a scratch size
* that will be automatically allocated for the group <groupId> at system
* startup, but only that is a preferred minimum scratch size to use for the
* first algorithm that gets created in the <groupId> group, if any.
*
* (An example: if algorithms A and B with the same groupId = 0 require 10K and
* 20K of scratch, and if SARAM_SCRATCH_SIZES[0] is 0, if A gets created first
* DSKT2 allocates a shared scratch area for group 0 of size 10K, as A needs.
* If then B gets to be created, the 20K scratch area it gets will not be
* shared with A's -- or anyone else's; the total internal memory use will be
* 30K. By contrast, if B gets created first, a 20K shared scratch will be
* allocated, and when A comes along, it will get its 10K from the existing
* group 0's 20K area. To eliminate such surprises, we set
* SARAM_SCRATCH_SIZES[0] to 20K and always spend exactly 20K on A and B's
* shared needs -- independent of their creation order. Not only do we save 10K
* of precious internal memory, but we avoid the possibility that B can't be
* created because less than 20K was available in the DSKT2 internal heaps.)
*
* Finally, note that if the codecs correctly implement the
* ti.sdo.ce.ICodec.getDaramScratchSize() and .getSaramScratchSize() methods,
* this scratch size configuration can be autogenerated by
* configuring Server.autoGenScratchSizeArrays = true.
*/
DSKT2.ALLOW_EXTERNAL_SCRATCH = false;
DSKT2.SARAM_SCRATCH_SIZES[GROUP_2] = 0x0000;
DSKT2.DARAM_SCRATCH_SIZES[GROUP_2] = 0x0000;
/*
* ======== DMAN3 (DMA manager) configuration ========
*/
/* First we configure how DMAN3 handles memory allocations:
*
* Essentially the configuration below should work for most codec combinations.
* If it doesn't work for yours -- meaning an algorithm fails to create due
* to insufficient internal memory -- try the alternative (commented out
* line that assigns "DDRALGHEAP" to DMAN3.heapInternal).
*
* What follows is an FYI -- an explanation for what the alternative would do:
*
* When we use an external memory segment (DDRALGHEAP) for DMAN3 internal
* segment, we force algorithms to use external memory for what they think is
* internal memory -- we do this in a memory-constrained environment
* where all internal memory is used by cache and/or algorithm scratch
* memory, pessimistically assuming that if DMAN3 uses any internal memory,
* other components (algorithms) will not get the internal memory they need.
*
* This setting would affect performance very lightly.
*
* By setting DMAN3.heapInternal = <external-heap> DMAN3 *may not* supply
* ACPY3_PROTOCOL IDMA3 channels the protocol required internal memory for
* IDMA3 channel 'env' memory. To deal with this catch-22 situation we
* configure DMAN3 with hook-functions to obtain internal-scratch memory
* from the shared scratch pool for the associated algorithm's
* scratch-group (i.e. it first tries to get the internal scratch memory
* from DSKT2 shared allocation pool, hoping there is enough extra memory
* in the shared pool, if that doesn't work it will try persistent
* allocation from DMAN3.internalHeap).
*/
var DMAN3 = xdc.useModule('ti.sdo.fc.dman3.DMAN3');
DMAN3.heapInternal = "INT_HEAP"; /* INT_HEAP is an internal segment */
DMAN3.heapExternal = "EXTALG_HEAP";
DMAN3.idma3Internal = false;
DMAN3.scratchAllocFxn = "DSKT2_allocScratch";
DMAN3.scratchFreeFxn = "DSKT2_freeScratch";
/* Next, we configure all the physical resources that DMAN3 is granted
* exclusively. These settings are optimized for the DSP on DM6446 (DaVinci).
*
* We assume PaRams 0..79 are taken by the Arm drivers, so we reserve
* all the rest, up to 127 (there are 128 PaRam sets on DM6446).
* DMAN3 takes TCC's 32 through 63 (hence the High TCC mask is 0xFFFFFFFF
* and the Low TCC mask is 0). Of the 48 PaRams we reserved, we assign
* all of them to scratch group 0; similarly, of the 32 TCCs we reserved,
* we assign all of them to scratch group 0.
*
* If we had more scratch groups with algorithms that require EDMA, we would
* split those 48 PaRams and 32 TCCs appropriately. For example, if we had
* a video encoder alg. in group 0 and video decoder alg. in group 1, and they
* both needed a number of EDMA channels, we could assing 24 PaRams and 16
* TCCs to Groups [0] and [1] each. (Assuming both algorithms needed no more
* than 24 channels to run properly.)
*/
DMAN3.paRamBaseIndex = 80; // 1st EDMA3 PaRAM set available for DMAN3
DMAN3.numQdmaChannels = 8; // number of device's QDMA channels to use
DMAN3.qdmaChannels = [0,1,2,3,4,5,6,7]; // choice of QDMA channels to use
DMAN3.numPaRamEntries = 48; // number of PaRAM sets exclusively used by DMAN
DMAN3.numPaRamGroup[GROUP_2] = 0; // number of PaRAM sets for scratch group 2
DMAN3.numTccGroup[GROUP_2] = 0; // number of TCCs assigned to scratch group 2
DMAN3.tccAllocationMaskL = 0; // assign no TCCs 0..31 for DMAN3
DMAN3.tccAllocationMaskH = 0xffffffff; // assign all TCCs 32..63 for DMAN3
/* The remaining DMAN3 configuration settings are as defined in ti.sdo.fc.DMAN3
* defaults. You may need to override them to add more QDMA channels and
* configure per-scratch-group resource sub-allocations.
*/
/*
* ======== RMAN (IRES Resource manager) configuration ========
*/
var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN');
RMAN.useDSKT2 = true;
RMAN.tableSize = 10;
/* The lock/unlock/set/getContext functions will default to DSKT2 */
the app remote.cfg:
/*
* ======== remote.cfg ========
*/
var platform = Program.platformName;
/* Bring in CE */
xdc.useModule('ti.sdo.ce.Engine');
/* Bring in UNIVERSAL support */
xdc.loadPackage('ti.sdo.ce.universal');
/* Assert we're on Linux */
if (Program.build.target.os != "Linux") {
throw ("Unsupported OS");
}
/* use and configure the osal. */
var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global');
osalGlobal.runtimeEnv = osalGlobal.DSPLINK_LINUX;
/* Configure IPC with settings consistent with the server config */
var common = xdc.loadCapsule('ti/sdo/ce/examples/buildutils/common_sys.cfg');
var Processor = xdc.useModule('ti.sdo.ce.ipc.dsplink.Processor');
Processor.heapId = common.MessageQ_heapMap["Ipc"];
Processor.sharedRegionId = common.SharedRegion_map["Ipc"];
// Set up logging
xdc.loadCapsule('ti/sdo/ce/examples/buildutils/common_log.cfg');
Would you tell me how to migrate from dm3730 to dm8148?