AM62A7: DDR Self Refresh

Maurice Lu

Part Number: AM62A7

Hi team,

We are studying the behavior of DRAM self refresh on AM62A EVM.
In TRM, there is a register called "PI_SELF_REFRESH_EN" (PI_145 bit [24]).
According to dtsi file, this bit has been set to 0.
Does that mean the system will never go to DDR self refresh mode, including during the boot up procedure?

Thanks.

B.R,
Maurice

4 months ago

0 JJD 4 months ago

TI__Guru* 94961 points

Hi Maurice, the PI is mainly used during initialization and training. You would use the controller to put the memory into self-refresh during normal operation. There are several ways to initiate self-refresh, either with a software command, or more of a hardware method which would perform self refresh operations automatically during idle periods. There are also several types of self refresh (short, long, etc) which depend on different events to exit self refresh.

What are you looking to achieve? Maybe i can help provide the easiest method.

Regards,

James

0 Maurice Lu 4 months ago in reply to JJD

Prodigy 160 points

Hi James,

Thanks for the feedback.
We would like to use hardware method to validate self refresh, could you guide me?
Also, how to make DRAM go into power down mode?

Thanks.
B.R,
Maurice

0 JJD 3 months ago in reply to Maurice Lu

TI__Guru* 94961 points

Hi Maurice, you would have to boot linux on the board and then follow one of the procedures described here: https://software-dl.ti.com/processor-sdk-linux/esd/AM62AX/11_01_07_05/exports/docs/linux/Foundational_Components/Power_Management/pm_low_power_modes.html to enter one of the low power modes.

DeepSleep would be simple enough to use if you just want to go into self refresh. What is different about power down mode? We typically support DeepSleep, which is a suspend to RAM mode that maintains CKE and RESET, and tri states other signals.

Regards,

James

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AM62A7: DDR Self Refresh