One of my colleagues asked me if he can use one of these joined ARM and DSP processors to replace his current FPGA+DSP setup. His main concern is can he shift data between each element and RAM as quickly as before.
He could not find a figure for the bandwidth of the L3 interconnect.
The traffic involved would be duplex up to around 30 Gbit/s, as a total of smaller flows between MAC, RAM, DSP and ARM.
It would seem within the capability of a bus which supports DD3, but he would like a document refrence?
Thanks in advance,
Chris
