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C667x Power Down Sequence

Courtney Cooley
Prodigy 235 points

Hello,

This may seem like a stupid question, but I am asking it anyway. The datasheet says that the power-down sequence should be the exact reverse of the power-up sequence. I have seen the other forum posts on this topic, including one in which my same questions was asked, but not explicitly answered.

My question is this: Do the clocks and other resets need to be included as part of the power down sequence, or are the power rails alone sufficient? In other words, can I disable the clocks and assert the resets as soon as POR or RESETFULL is asserted, then sequence through turning off each power rail. Or should I sequence the resets and clocks as well?

Thank you very much.

-Courtney

  • 0
    TI__Mastermind 42545 points

    Hi Courtney,

    The clocks and resets do not have to be explicitly controlled in reverse order during the power down sequence but you will need to disable anything driving an IO once the IO voltage is no longer present.  For the reset signals that IO voltage is the 1.8V, for the clocks it's the 1.0V AVS voltage.  Once the 1.8V is removed from the device then all IOs connected to other devices must either be driven to a low state or the drivers must be powered down.  The same is true for the clock sources.

     

  • 0 in reply to Bill Taboada
    Prodigy 235 points

    Thanks Bill.

    -Courtney