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DRA821U-Q1: SGMII timing is out of PHY spec

Max Chen1
Expert 1075 points

Part Number: DRA821U-Q1

Hi,

we use 1Gb ETH PHY to SoC via SGMII, the PHY spec TXD rise/fall time (20% to 80%): 210ps max, but we get 350ps on both transmitter(PHY) and receiver(SoC) sides.

Q1: what is the impedance at receiver side, 100ohm diff, right?

Q2: what is the timing required for SoC receiver side?

Q3: can you provide detail timing for SoC's SGMII?

image.png

Thanks

Max

 

  • 0
    TI__Guru 64290 points

    Hi Max,

    Yes, the differential impedance is 100ohm for the differential TX/ RX pair.

    couple of points on the transition time ( rise/fall times):

    1) They are measured at the output of the SoC pads; in order to do that you would have to de-embed to remove the effects of the on board traces and cables.

    2) The transition time is a recommended value to be b/w 60- 320ps and not a compliance requirement - So I would imagine that you should be in within the recommended values once you remove the trace effects. 

    It is also sometimes ideal to have higher transition time to not have EMC in general.