AM62P: AM62P: SPI inter-frame interval problem

Hi,

I am going to review this thread in about an hour and get back to you before end of today.

Regards,

Vaibhav

Hi,

Could you try playing with the field in SysConfig > MCSPI > Chip-select TCS 

Regards,

Vaibhav

Hi

I have try two TCS configurations, and the peripheral fails to respond properly under both. As shown in P1, the delay is set to 3.5 clock cycles delay. As shown in P2, the delay is set to 0.5 clock cycles delay. As shown in P3, these two configuration only affect the time between the CS assertion and first clock edge or CS removal and last clock edge, do not influence the CS idle time between frames. I think the CS idle time is the root cause.

P.1 

P.2 

P.3 

As i mentioned before, when i insert a while() function into the SDK transmit function MCSPI_fifoWrite16() , the CS idle time was increased to 2.8us. With this adjustment, the peripheral responds properly.

Hi,

Can you please share your Peripheral's datasheet and where it states that there should be time between CS Toggling.

This would help me create a feature request/add-on as this is not a bug in the driver but can be possibly a good add on.

Looking forward to your response.

Regards,

Vaibhav

Hi

The official link to the Peripheral's datasheet is provided below, and the SPI timing characterization is located on page 15. However, the description of CS idle time is not found in this datasheet.

product.tdk.com/.../ds-000481-iam-20680ht-v1.1.pdf