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SK-AM62-LP: AM62X: Question Regarding GIC Interrupt Triggers (Level/Edge)

eito kotake
Prodigy 20 points

Part Number: SK-AM62-LP

I am currently developing using the SK-AM62-LP and have implemented a function to set the FreeRTOS GIC interrupt trigger (level/edge).
I set the initial values ​​by referring to the AM62x TRM, but I could not find information about the following interrupts within the TRM. Therefore, I would appreciate it if you could advise me on appropriate interrupt triggers for these interrupts.
Also, if you have any documentation that contains information on appropriate interrupt triggers for these interrupts, I would be very grateful if you could provide it.

 

interrupt.png

  • 0
    TI__Intellectual 1430 points

    Hello,
    Thank you for your query. The concerned expert is Out of Office due to **TI India** Holiday.
    Please expect a delay in response. We appreciate your patience and understanding.

    Best regards,
    TI E2E Support Team
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  • 0
    TI__Guru 63318 points

    Which version of TRM are you referring to? I am not able to find the above table in the AM62x TRM. 

    Regards,

    Tushar

  • 0 in reply to Tushar Thakur
    Prodigy 20 points

    Thank you for your reply.

    The attached image is a cropped version (Literature Number: SPRUIV7B MAY 2022 – REVISED SEPTEMBER 2023).

    In the latest version (Literature Number: SPRUIV7C MAY 2022 – REVISED NOVEMBER 2025), the instance name GICSS0 in Table 10-7. Interrupts (Inputs) should be relevant. Even in this version, I was unable to find the appropriate interrupt trigger information for the interrupt I extracted in the previous image.

  • 0 in reply to eito kotake
    TI__Guru 63318 points

    The image you shared above talks about the CMP_EVENT_INTRROUTER, DMSS_INTAGGR, GPIOMUX_INTRROUTER, RESET, SA3SS, SMS, DDR and ESM.

    You can find the details for the above mentioned interrupts in TRM section 4 Module Intergration.

    e.g. For CMP_EVENT_INTRROUTER refer to section 4.3.4.2 ICSSM Integration. Please refer image below.

    Regards,

    Tushar

  • 0 in reply to Tushar Thakur
    Prodigy 20 points

    Thank you for your reply.

    I would appreciate it if you could clarify a few points.

    First, is the section you showed in the image detailed information for "GICSS0_SPI_IN_48" listed in Table 10-7. Interrupts (Inputs)?

    Regarding other GIC SPI interrupts, for example, with "GICSS0_SPI_IN_127," the "Destination Interrupt Input" column in the table in the image shows "GICSS0_spi_127," so I was able to understand that it is related to "GICSS0_SPI_IN_127."

    However, with "GICSS0_SPI_IN_48," the "Destination Interrupt Input" column was in a different format than GICSS0_spi_xxx, so I couldn't understand why the section you showed in the image is related. Therefore, I would like to know which part I should look at to make the connection.

    Currently, I am referring to 4 Module Integration and looking for information on interrupt triggers corresponding to interrupts. We were able to find detailed information for entries in the table where the "Destination Interrupt Input" column is in the format GICSS0_spi_xxx, but the information for the others remains unknown.

    The specific interrupts whose details are unknown are listed below. (Excerpted from Table 10-7. Interrupts (Inputs))

    -----------------------------------------------------------------
    GICSS0_SPI_IN_48 ~ GICSS0_SPI_IN_63
    GICSS0_SPI_IN_104 ~ GICSS0_SPI_IN_107
    GICSS0_SPI_IN_110 ~ GICSS0_SPI_IN_113
    GICSS0_SPI_IN_133
    GICSS0_SPI_IN_143 ~ GICSS0_SPI_IN_144
    GICSS0_SPI_IN_151
    GICSS0_SPI_IN_160 ~ GICSS0_SPI_IN_161
    GICSS0_SPI_IN_172
    GICSS0_SPI_IN_176 ~ GICSS0_SPI_IN_177
    GICSS0_SPI_IN_180 ~ GICSS0_SPI_IN_182
    GICSS0_SPI_IN_198
    GICSS0_SPI_IN_201 ~ GICSS0_SPI_IN_203
    GICSS0_SPI_IN_256
    -----------------------------------------------------------------

    I was unable to find detailed information about these interrupts, so I apologize for asking so many questions, but I would be grateful if you could tell me about the appropriate interrupt triggers for these interrupts.

    Also, if there is a section that contains detailed information but I have overlooked it due to my poor search skills, I would be very grateful if you could tell me the specific location where it is written.

  • 0 in reply to eito kotake
    TI__Guru 63318 points

    Please see the below explanation.

    eito kotake said:
    GICSS0_SPI_IN_48 ~ GICSS0_SPI_IN_63

    The above interrupts lines are connected to the CMP_EVENT_INTROUTER and the CMP_EVENT_INTROUTER is connected to the ICSSM module.

    Please refer below image.

    How can I read those connection?

    We will take one interrupt line as an example. Let say we have to map the GICSS0_SPI_48 line.

    To map the above interrupt line, please check the Interrupt output section to check which interrupt output line is connected to GICSS0_SPI_48.

    Once you figure out which interrupt line is connected to GICSS0_SPI_48, Check for the same interrupt line in the Interrupts Input section.

    From the above image the line we need to check is CMP_EVENT_INTROUTER0_OUTP_OUT_0. Now search for CMP_EVENT_INTROUTER0_IN_IN_0 line in the interrupts inputs section. Remember the Interrupts (Output) section will have *OUT suffix but the Interrupts (Inputs) will have IN as suffix.

    Refer the image below.

    Now from above we know that CMP_EVENT_INTROUTER0_IN_IN_0 is connected to the ICSSM0_PR1_HOST_INTR_REQ_OUT_0.

    Now this indicates that the source of interrupt is coming from ICSSM0. Go to the module integration section and check for the interrupt name. The interrupt name will not have any suffix like IN or OUT.

    The interrupt name we got from above is ICSSM0_PR1_HOST_INTR_REQ_0 which is pulse interrupt.

    Please refer image below.

    Hope the above information helps. Let us know if you still need help.

    Regards,

    Tushar

  • 0 in reply to Tushar Thakur
    Prodigy 20 points

    Thank you for your reply.

    I was able to find some of the interrupts by referring to the information you provided.

    However, I was unable to find details about the following interrupts using the search method you described. Could you please tell me about the appropriate interrupt triggers for these interrupts?

    -----------------------------------------------------------------
    GICSS0_SPI_IN_112 ~ GICSS0_SPI_IN_113
    GICSS0_SPI_IN_160 ~ GICSS0_SPI_IN_161
    GICSS0_SPI_IN_177
    GICSS0_SPI_IN_203
    GICSS0_SPI_IN_256
    -----------------------------------------------------------------


    I have one more question.

    The following interrupts were defined in "Table 10-12. GIC Interrupt Connection" within "Literature Number: SPRUIV7B MAY 2022 – REVISED SEPTEMBER 2023," but the corresponding numbers appear to be missing in "Table 10-7. Interrupts (Inputs)" within "Literature Number: SPRUIV7C MAY 2022 – REVISED NOVEMBER 2025." Could these be interrupts that were removed in the version update?

    If these interrupts haven't been deleted, I would appreciate it if you could also tell me the appropriate interrupt triggers for them.

    -----------------------------------------------------------------
    gicss0.spi.110
    gicss0.spi.111
    gicss0.spi.143
    gicss0.spi.144
    gicss0.spi.176
    gicss0.spi.198

    -----------------------------------------------------------------

  • 0 in reply to eito kotake
    TI__Guru 63318 points
    eito kotake said:
    However, I was unable to find details about the following interrupts using the search method you described. Could you please tell me about the appropriate interrupt triggers for these interrupts?

    Looks like the details for mentioned interrupts are not in the TRM. I will check this internally and update. Please allow some time to revert back.

    eito kotake said:
    If these interrupts haven't been deleted, I would appreciate it if you could also tell me the appropriate interrupt triggers for them.

    The interrupts which are not listed in the TRM are reserved and should not be configured/used by the user application.

    Regards,

    Tushar

  • 0 in reply to eito kotake
    TI__Guru 63318 points

    Hi Eito,

    eito kotake said:
    GICSS0_SPI_IN_112 ~ GICSS0_SPI_IN_113

    I did check the interrupts are coming from the Interrupt Aggregators. The interrupt aggregator are level sensitive on output and level or edge sensitive on input. This means the input to this interrupt aggregators may be edge or level trigger, but the output from this aggregators are always level trigger.

    Please refer below image from TRM.

    Regards,

    Tushar

  • +1 in reply to eito kotake
    TI__Guru 63318 points
    eito kotake said:
    GICSS0_SPI_IN_160 ~ GICSS0_SPI_IN_161
    GICSS0_SPI_IN_177
    GICSS0_SPI_IN_203
    GICSS0_SPI_IN_256

    The details related to this interrupts are not available in the public TRM. I have checked this internally in the team and below are the interrupt trigger types.

    The interrupt number 160, 161, 177, 256 are of type level trigger.

    The interrupt number 203 is of type pulse trigger.

    Regards,

    Tushar

  • 0 in reply to Tushar Thakur
    Prodigy 20 points

    Thank you.

    This has solved the problem.