TMS320C6655: GPIO INTERRUPT

Hi,

Fartine Tripoli said:

How to handle multiple gpio pin interrupts in TMS320C6655 processor at rising edge simultaneously so that one interrupt would not affect other isr?

Within a GPIO bank, simultaneous pin events are latched in SET_RIS_TRIG as a bitmask and generate a single bank interrupt; the ISR must decode and service each pin in software. Across banks, each bank issues a separate interrupt via the CIC, and the C66x CorePac resolves simultaneous arrivals using fixed priority (INT4 highest). Lower-priority interrupts remain pending and are serviced after the active ISR completes (no default nesting).

You can also refer the following files in the sdk for the interrupt configurations:

pdk_c665x_2_0_16/packages/ti/csl/cslr_gpio.h
pdk_c665x_2_0_16/packages/ti/csl/csl_gpioAux.h
pdk_c665x_2_0_16/packages/ti/csl/example/gpio/gpio_interrupt/main.c
pdk_c665x_2_0_16/packages/ti/csl/soc/c6657/src/csl_device_interrupt.h
pdk_c665x_2_0_16/packages/ti/csl/soc/c6657/src/csl_gpioGetBaseAddress.c

Regards,
Shabary S Sundar

Can you share a pseudocode for GPIO 14,15,16 interrupts using csl functions?

Hi Fartine,

Hi betsy,

Does GPIO pin 16 comes under bank 1?. Does SET_RIS_TRIG can be used to latch both primary and secondary GPIO pins? Should I use single isr function to service all the pin interrupts?

Regards,

Fartine.