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GPIO interrupt not triggering

Guru 15580 points

I am trying to use GPIO[4] as an external interrupt. I have set

1. DIR4 as input (0)

2. INTEDGE4 = 1

3. INTEN4 = 1

I then apply my external stimulus going from logic 0 to logic 1. However, the INTFLG4 does not get set. What could I be doing wrong? Below is a snapshot of the GPIO registers showing the proper settings, but no interrupt flag. 

Could someone shed some light on this?

GPIO
IODIR1 0xD801 Memory Mapped Register: GPIO data direction bits that configure the general purpose IO pins 0 - 15 as either inputs or outputs
DIR15 1 - Set Direction of GPIO Pin 15
DIR14 1 - Set Direction of GPIO Pin 14
DIR13 0 - Clear Direction of GPIO Pin 13
DIR12 1 - Set Direction of GPIO Pin 12
DIR11 1 - Set Direction of GPIO Pin 11
DIR10 0 - Clear Direction of GPIO Pin 10
DIR9 0 - Clear Direction of GPIO Pin 9
DIR8 0 - Clear Direction of GPIO Pin 8
DIR7 0 - Clear Direction of GPIO Pin 7
DIR6 0 - Clear Direction of GPIO Pin 6
DIR5 0 - Clear Direction of GPIO Pin 5
DIR4 0 - Clear Direction of GPIO Pin 4
DIR3 0 - Clear Direction of GPIO Pin 3
DIR2 0 - Clear Direction of GPIO Pin 2
DIR1 0 - Clear Direction of GPIO Pin 1
DIR0 1 - Set Direction of GPIO Pin 0
IODIR2 0x0403 Memory Mapped Register: GPIO data direction bits that configure the general purpose IO pins 16 - 31 as either inputs or outputs
IOINDATA1 0x0790 Memory Mapped Register: Data bits used to monitor the state of GPIO pins 0 -15 when configured as inputs.
IN15 0 - Clear Status of GPIO Bit 15
IN14 0 - Clear Status of GPIO Bit 14
IN13 0 - Clear Status of GPIO Bit 13
IN12 0 - Clear Status of GPIO Bit 12
IN11 0 - Clear Status of GPIO Bit 11
IN10 1 - Set Status of GPIO Bit 10
IN9 1 - Set Status of GPIO Bit 9
IN8 1 - Set Status of GPIO Bit 8
IN7 1 - Set Status of GPIO Bit 7
IN6 0 - Clear Status of GPIO Bit 6
IN5 0 - Clear Status of GPIO Bit 5
IN4 1 - Set Status of GPIO Bit 4
IN3 0 - Clear Status of GPIO Bit 3
IN2 0 - Clear Status of GPIO Bit 2
IN1 0 - Clear Status of GPIO Bit 1
IN0 0 - Clear Status of GPIO Bit 0
IOINDATA2 0x0000 Memory Mapped Register: Data bits used to monitor the state of GPIO pins 16 - 31 when configured as inputs.
IOOUTDATA1 0x5001 Memory Mapped Register: Data bits used to control the level of the GPIO pins 0 - 15 which are set as outputs
IOOUTDATA2 0x0402 Memory Mapped Register: Data bits used to control the level of the GPIO pins 16 - 31 which are set as outputs
IOINTEDG1 0x0010 Memory Mapped Register: Data bits used to set the Interrupt trigger of GPIO pins 0 - 15 to rising or falling edge if the GPIO has interrupt enabled. 0 = rising edge; 1 = falling edge
INTEDG15 0 - Clear Edge select for GPIO 15
INTEDG14 0 - Clear Edge select for GPIO 14
INTEDG13 0 - Clear Edge select for GPIO 13
INTEDG12 0 - Clear Edge select for GPIO 12
INTEDG11 0 - Clear Edge select for GPIO 11
INTEDG10 0 - Clear Edge select for GPIO 10
INTEDG9 0 - Clear Edge select for GPIO 9
INTEDG8 0 - Clear Edge select for GPIO 8
INTEDG7 0 - Clear Edge select for GPIO 7
INTEDG6 0 - Clear Edge select for GPIO 6
INTEDG5 0 - Clear Edge select for GPIO 5
INTEDG4 1 - Set Edge select for GPIO 4
INTEDG3 0 - Clear Edge select for GPIO 3
INTEDG2 0 - Clear Edge select for GPIO 2
INTEDG1 0 - Clear Edge select for GPIO 1
INTEDG0 0 - Clear Edge select for GPIO 0
IOINTEDG2 0x0000 Memory Mapped Register: Data bits used to set the Interrupt trigger of GPIO pins 16 - 31 to rising or falling edge if the GPIO has interrupt enabled. 0 = rising edge; 1 = falling edge
IOINTEN1 0x0010 Memory Mapped Register: Data bits used to enable the Interrupts of GPIO pins 0 - 15. 0 = Interrupt disabled; 1 = Interrupt enabled.
INTEN15 0 - Clear Interrupt enable for GPIO 15
INTEN14 0 - Clear Interrupt enable for GPIO 14
INTEN13 0 - Clear Interrupt enable for GPIO 13
INTEN12 0 - Clear Interrupt enable for GPIO 12
INTEN11 0 - Clear Interrupt enable for GPIO 11
INTEN10 0 - Clear Interrupt enable for GPIO 10
INTEN9 0 - Clear Interrupt enable for GPIO 9
INTEN8 0 - Clear Interrupt enable for GPIO 8
INTEN7 0 - Clear Interrupt enable for GPIO 7
INTEN6 0 - Clear Interrupt enable for GPIO 6
INTEN5 0 - Clear Interrupt enable for GPIO 5
INTEN4 1 - Set Interrupt enable for GPIO 4
INTEN3 0 - Clear Interrupt enable for GPIO 3
INTEN2 0 - Clear Interrupt enable for GPIO 2
INTEN1 0 - Clear Interrupt enable for GPIO 1
INTEN0 0 - Clear Interrupt enable for GPIO 0
IOINTEN2 0x0000 Memory Mapped Register: Data bits used to enable the Interrupts of GPIO pins 16 - 31. 0 = Interrupt disabled; 1 = Interrupt enabled.
IOINTFLG1 0x0000 Memory Mapped Register: Data bits used to monitor which GPIO Interrupt was triggered. For GPIO pins 0 - 15
INTFLG15 0 - Clear This register latches the corresponding I/O pin(s) that triggered an interrupt. The flag is cleared by setting the corresponding bit. The interrut signal to the CPU will be kept low until all flag bits are cleared.
INTFLG14 0 - Clear
INTFLG13 0 - Clear
INTFLG12 0 - Clear
INTFLG11 0 - Clear
INTFLG10 0 - Clear
INTFLG9 0 - Clear
INTFLG8 0 - Clear
INTFLG7 0 - Clear
INTFLG6 0 - Clear
INTFLG5 0 - Clear
INTFLG4 0 - Clear
INTFLG3 0 - Clear
INTFLG2 0 - Clear
INTFLG1 0 - Clear
INTFLG0 0 - Clear
IOINTFLG2 0x0000 Memory Mapped Register: Data bits used to monitor which GPIO Interrupt was triggered for GPIO pins 16 - 31.

  • Hi,

    There is an example to use GPIO as an external interrupt source. Please check CSL2.5 from http://software-dl.ti.com/dsps/dsps_public_sw/dsps_swops_houston/C55X/CSL-c55x-lowpower-versions.htm. It's under \c55xx_csl\ccs_v4.0_examples\gpio\CSL_GPIO_InputPinExample.

    Regards,

    Hyun

  • Hyun,

    I have been working with the CSL example for two days. I am very familiar with how it SHOULD work. Can you explain why (in my original post) all of the registers are properly set, but the interrupt is not triggering, and the interrupt flag is not set? How can this happen? I can watch the GPIO4 input pin go from zero to one, yet the int flag4 is not set. What could possibly cause this?

  • Hi,

    Did you set Pin muxing for GPIO4?

    /* Pin muxing for GPIO 4 and 11 Pin */
    CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_SP0MODE, MODE2);
    CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_SP1MODE, MODE2);
    Regards,
    Hyun
  • I am not using the CSL functions, but the modes are properly set by my code per the register capture below:

    EBSR 0x5900 Memory Mapped Register: External Bus Selection Register
    _RESV_1 * Reserved.
    PPMODE 101 - MODE5 Parallel port mode bits. These bits control the pin muxing on the parallel port.
    SP1MODE 10 - MODE2 Serial port 1 mode bits. These bits control the pin muxing on serial port 1.
    SP0MODE 01 - MODE1 Serial port 0 mode bits. These bits control the pin muxing on serial port 0.
    _RESV_5 ** Reserved.
    A20_MODE 0 - MODE0 This bit controls the pin multiplexing on EM_A[20].
    A19_MODE 0 - MODE0 This bit controls the pin multiplexing on EM_A[19].
    A18_MODE 0 - MODE0 This bit controls the pin multiplexing on EM_A[18].
    A17_MODE 0 - MODE0 This bit controls the pin multiplexing on EM_A[17].
    A16_MODE 0 - MODE0 This bit controls the pin multiplexing on EM_A[16].
    A15_MODE 0 - MODE0 This bit controls the pin multiplexing on EM_A[15].

    SPOMODE 01 activates GP[5:4] as IO pins.

    Any other thoughts?

  • C'mon guys. I'm dead in the water! Will someone please pay attention to this issue?

    To summarize, as you can see from the register snapshot above, I have correctly set GPIO4 as an input to trigger an interrupt on a rising edge. However, when I apply a positive-going signal in the GPIO4 input, the IOINDAT4 data shows up, but  the INTFLG4 does not get set. WHAT COULD BE CAUSING THIS?

  • Beware the negative logic.....:)

    Thanks for all the help.:(