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AM62D-Q1: Regarding the LPDDR4 routing delay value

O.H
Mastermind 7270 points

Part Number: AM62D-Q1

Hi experts,

My customer has started designing a board using the AM62D. Regarding the LPDDR4 routing delay value described in "AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines (sprad66b.pdf)", there is a description: "LP4_ACRS1 Propagation delay of net class CK0 (RSAC1 + RSAC2): Max 250ps".
 
Q1: What kind of impact will occur if this 250ps is exceeded?
Currently, the routing has been completed, and the calculated value is about 260ps. Although amplitude attenuation occurs as the routing becomes longer, I believe the phase is not a problem. Is this correct? Other routing conditions are assumed to be satisfied.
 
Q2: Is it acceptable to judge 250ps based on the calculated value (package + surface delay + internal layer delay + via delay)?
When calculated using a simulator with IBIS, the value increases by about 100~200ps from the calculated value (because rise and fall delays are added), making it difficult to keep it within 250ps.
 
Best regards,
O.H
  • +1
    TI__Guru* 96101 points

    As the note mentions, " This value can be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation."    I would recommend performing board level simulations if you violate any of the app note recommendations.  Yes, the 250ps is based on the full propagation delay (package, board trace, and vias)

    Regards,

    James

  • 0 in reply to JJD
    Mastermind 7270 points

    Hi james,

    Thank you for your reply. I understood. If any further questions arise, I will create a new thread.

    Best regards,
    O.H