Part Number: TDA4VE-Q1
Other Parts Discussed in Thread: AM68A
Hi,
I have a project going using a J721S2 Jacinto multicore processor. The DSP cores are running projects ported from a previous device that uses C66 DSPs. The code is running normally, but processing time per iteration is varying from one moment to the next. I think I may be able to smooth this out by giving priority to DSP cores in the MSMC for memory access as described in chapter 8 of the TRM SPRUJ28F - J721S2 AM68A TRM.pdf.
Specifically how can I adjust the cores' priority as talked about in section "8.1.2.6 MSMC Resource Arbitration"?
How can I set the DSP cores to use QoS thread 2 "real-time" (Table 8-8). The Note claims "There is no software control over the MSMC QoS hardware" - what does this mean? How is the QoS set if there isn't control?
Is this something done with direct register access, or is there an API that's part of the SDK/PDK?
Thanks,
Matt
