AM2434: AM2434 Clock timings help

Hi Chris,

I ran a test on my EVM to verify this, the PMU cycle counter is getting correct results for me.

Could you please check, what CPU frequency is configured for R5 and whether you are using the correct frequency for your calculation?

Best Regards,

Meet.

Hi Meet,

The hardware platform is the TMDS243EVM.  CCS version is 20.4.1.4.  MCU+ SDK version is 11.01.00.19.  The project I'm using is based on the "pcie_benchmark_rc" example and the clock is configured in System Configuration as shown in the attached image.  My conversion from PMU cycle counts to elapsed time assumes an 800 MHz CPU clock.  I used a toggling LED and called "ClockP_sleep(10U)" between toggles.  Timing the LED "on" duration with a stopwatch agreed with the PMU calculation of ~5sec versus the ClockP_sleep input argument of ~10sec.  Is there maybe another timer configuration I'm missing?

Shawn

Hi Shawn,

Apologies for the delay, let me run one more test using 11.1. This might not cause any issue but are you using C++ for this? We don't have any examples based on C++ for PCIe in the MCU+SDK could you provide more background on this.

Best Regards,
Meet.

I am using C++ for newer code but the sample projects setup the SDK as a linked "nortos" C library so I wasn't expecting the compiler to affect it.

I tried this using 11.1 as well, I still observe expected results. I am attaching empty.c file which I used to to test this on my EVM, can you port the same to empty example on R5F0-0 in the SDK and share the results with me.

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#include <stdio.h>
#include <kernel/dpl/DebugP.h>
#include <drivers/pmu.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"

/*
 * This is an empty project provided for all cores present in the device.
 * User can use this project to start their application by adding more SysConfig modules.
 *
 * This application does driver and board init and just prints the pass string on the console.
 * In case of the main core, the print is redirected to the UART console.
 * For all other cores, CCS prints are used.
 */

void empty_main(void *args)
{

    uint32_t elapsed_cycles = 0;
    uint64_t total_cycles = 0;

    /* Open drivers to open the UART driver for console */
    Drivers_open();
    Board_driversOpen();
#if defined(AMP_FREERTOS_A53)
    DebugP_log("All tests have passed on a53_core%d!!\r\n", Armv8_getCoreId());
#else

    for(uint8_t i = 0; i < 25; i++){

    CSL_armR5PmuResetCycleCnt();

    // elapsed_cycles = CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM);

    ClockP_sleep(1);

    elapsed_cycles = CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM);
    total_cycles += elapsed_cycles;

    }


    DebugP_log("Average Elapsed cycles:%d\r\n",total_cycles/25);
#endif 
    Board_driversClose();
    Drivers_close();
}

Thanks Meet, that was helpful.  Results below.  I'm going to look through the two sysconfig files and see if anything is different.

Empty main file:

MAIN_Cortex_R5_0_0: Average Elapsed cycles:799970820

Main file for my project:

MAIN_Cortex_R5_0_0: Average Elapsed cycles:399877566

Hi Shawn,

Shawn Mason said:

Thanks Meet, that was helpful.  Results below. 

That's good to know. This indicates there could be some variation between the default clock configuration and your project. Please feel free to reach out if you discover anything.

Best Regards,

Meet.

I don't think it's the main 800 MHz core clock.  I timed when the printout occurs and when I get half the clock cycles it also prints in half the time, so that appears to checkout.  Maybe it has something to do with the timers used by the ClockP DPL module.  I don't see any obvious differences in the two projects in the generated SysConfig files.  Any ideas?

Hi Meet,

One more data point.  I created a new project using the Project Wizard and based on the NORTOS "pcie_benchmark_rc".  This was the basis for our custom project.  I copied your code into the main function and replicated the issue I'm seeing.  I'd be curious if you can recreate this problem and what you think the issue might be.

MAIN_Cortex_R5_0_0: Average Elapsed cycles:399908578

Shawn

Thanks Meet!  I had been so focused on the clock and interrupts that I had not thought to check the MPU configuration.  I verified both Strongly Ordered and Device configurations correct the issue.