J784S4XEVM: main0 R5 timer capture mode is not working as expected

Hi team,

They moved their app from an MCU R5F core to the main0 R5 core0 but are still having issues with their interrupt triggering properly. Their configuration is accessible in the drive link shared which I reviewed and everything appears to be correct. Could you double check the configuration and advise on anything else that may be causing the interrupt not to trigger?

Best,

Luke

Hi Luke,

Is this issue observed on TIMER4 only? Can we change the timer instance to verify this once?

Regards,

Anil

Luke said:

Currently only TIMER4 is connected to a pin.  Is it because the GPIO0 module is not powered on or clocked ? I changed the pin to GPIO, the pin state is not toggling. A new version of test results is uploaded in the box

Hi JIm,

Where the new version of test results is uploaded?

GPIO0 (configuring TIMER4 as GPIO0) is not toggling?

Regards,

Anil

Yes,, same document name updated with GPIO test.

My concerns is during test, EMU0 =0, EMU1=1, this will hold main0 r5 in reset. I worried that it will hold all other processors in reset. The board initialization may not be done when I load my app to main0 r5 and start my application

- Try loading the app on other core (MAIN1/R51).
- Try disabling EMU0/EMU1. 

If still observing the issue, we can have the call.

Regards,

Anil

test report with suffix __Apr_07 uploaded.

additional info:  the pin state for those inputs are not toggling, usually the pin state should be toggling fast

GPIO0 clock is not initialized ?

Thanks

Hi Jim,

If we are configuring GPIO pin as input and want to read GPIO pin state then:

- if the pin is connected to VCC then we need to PULLDOWN GPIO pin
- If the pin is connected to GND then we need to PULLUP GPIO Pin

Regards,

Anil

I modified EVM and test the capture mode. It works correctly. So it is my hardware issue, not software configuration. I have another question: When using the capture mode, every time the capture is happening, TCAR1 and/or TCAR2 captured value: 1: restart from 0 ? 2:  keep previous reading counts, and add on top of it?   If it is option 2, is the way to configure and force it to retick from 0 ?

In the EVM board I have following issue:

1)  When I set TCM=3 to capture on both edges, how can I know the pulse sequence when the interrupt is triggered?  rising ->falling ->rising verse falling--rising--falling ?   

2) can I always assume that TCAR1 latches on rising edge and TCAR2 latches on falling edge?

3) I can not set READ_MODE bit in TSICR register, I can only set POSTED bit at that register

1) But if we set TCM = 3, TCAR1 and TCAR2 registers store the values when the interrupt happens, They will not tell the pulse sequence (raising->falling or falling->raising)

And at the time of interrupt we need to read the timer input pin status register to know the sequence.(raising->falling or falling->raising)

2) No, TCAR1 and TCAR2 registers only stores the value of first event or second event.

- If configured for raising edge then TCAR1 and TCAR2 registers capture the timer values in raising edge.
- if configured for falling edge then TCAR1 and TCAR2 registers capture the timer values in falling edge.

and the rising edge, falling edge, or both, can be selected from the TIMER_TCLR[9-8] TCM bit.

As the J784S4 TRM says,
 - If the TIMER_TCLR[13] CAPT_MODE bit is 0, on the first enabled capture event, the value of the
counter register is saved in the TIMER_TCAR1 register

 - If the TIMER_TCLR[13] CAPT_MODE bit is 1, on the first enabled capture event, the value of the counter
register is saved in the TIMER_TCAR1 register, and on the second enabled capture event, the value of the
counter register is saved in the TIMER_TCAR2 register.

so we can conclude when the CAPT_MODE bit = 1, it is used to measure the time between TCAR1 and TCAR2.

Regards,

Anil

why I can not set READ_MODE bit in TSICR register, I can only set POSTED bit at that register ?

If we set the POSTED bit to 0x1, then we cant set the READ_MODE bit because, both read and write operations are expected in posted mode.