Switching EBSR PPMODE while the C5505 is running

You can select LIDD mode 6800 or mode 8080, in which those LCD controller signals are active-low. However, you may get false strobes on those pins when switching between PPMODE 1 and 5.

Thanks Cong, do you or others know what the state of these pins would be if I used the clock gating register to hold the LCD controller in Idle?

Hi John,

Let me try to answer your questions.

John Mackinnon said:

At boot time the bootloader queries both PPMODE 1 & 5 configurations so it should (yes?) find the mode 5 boot flash and boot from it.

Correct, the device can be connected to either valid pin-mapping for SPI (there are two distinct pin-mappings available). The bootloader attempts to communicate on each SPI pin-mapping, one at a time.

John Mackinnon said:

We will use two EBSR.PPMODE modes 1 and 5

C5505 Datasheet - 4.6.1 External Bus Selection Register (EBSR)

"Before modifying the values of the external bus selection register, you must clock gate all affected peripherals through the Peripheral Clock Gating Control Register. After the external bus selection register has been modified, you must reset the peripherals before using them through the Peripheral Software Reset Counter Register."

John Mackinnon said:

The real question I have is this. In mode 1 the pins that connect to the 4 SPI device chip selects are the SPI peripheral CS0-CS3 signals. In mode 5 these same pins are connected to four of the LCD controller signals (LCD_CS0_E0, LCD_CS1_E1, LCD_RW_WRB,LCD_RS) which are all strobe outputs.

So, can I manage the clock gating/reset/programming of the LCD controller so that these four signals remain a steady logic high?

Good question! All four of these pins are outputs from the LCD peripheral, so you need to ensure they are driving high.

I'm not certain what would happen if you switched the EBSR and left the LCD peripheral clock gated - what state are the pins? A good experiment.

Likely you'll have to configure the LCD peripheral so that these pins are logic high. Once they are configured to output high, you could clock gate the LCD peripheral and it will keep its state.

Since a LCD peripheral reset is required after modifying the EBSR, these pins might reset low and need to be configured high - need to check. However, I'm not sure if you need to reset the peripheral if it is clock-gated and not used... maybe just configure it once at the beginning of the program, then clock gate it forever.

Regardless, when PPMODE = 5, SPI_CLK, SPI_TX, SPI_RX, and SPI_CS0 are on completely different pins as the SPI signals when in PPMODE = 1. No SPI CLK will arrive at the 4 SPI devices tied to the pins of PPMODE = 1.

Are you concerned about providing a false chip select to an inactive SPI device?

I can further investigate the behavior - this is a new utilization of the SPI pins for me.

Regards,
Mark

John Mackinnon said:

Thanks Cong, do you or others know what the state of these pins would be if I used the clock gating register to hold the LCD controller in Idle?

Hi John,

I have no idea about that. Anyway, why do you really need HI state on these pins? Even at active CS, the SPI device cannot work without SPI_CLK.

Regards,

Cong-Van