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GPMC Unintentional Prefetching/Caching Behavior

Barry Rougeau
Prodigy 40 points
Other Parts Discussed in Thread: OMAP3530

I have a Spartan 6 FPGA wired to an OMAP3530 via the GPMC as chip select two. I've written a simple character driver for the GPMC that implements open and mmap file operations. When I mmap the device memory in userland and then perform a single 16-bit write to it, the bus activity seen by the Spartan via ChipScope is correct. However, when I perform a single 16-bit read, the bus activity shows 32 consecutive reads with incrementing addresses. The value returned to the software is correct, but this behavior implies that I've enabled some sort of prefetching or DMA, when I've specifically disabled prefetching via register GPMC_CONFIG1 and have not setup any DMA in my code.

Here is my register configuration, which I print out within the driver each time the device is opened.


GMPC_CONFIG1: 0x04001203 (single access, asynchronous read/write, etc)

GPMC_CONFIG2: 0x001F1F04

GPMC_CONFIG3: 0x00080804

GPMC_CONFIG4: 0x180F180F

GPMC_CONFIG5: 0x00181F1F

GPMC_CONFIG6: 0x940A0400

Also, I even call gpmc_prefetch_reset in the driver each time the device is opened and print the prefetch registers which are all zeroed out.

So overall my question is why is this prefetching behavior happening? Is it my GPMC configuration or could it be the OMAP cache hardware?

  • 0
    Prodigy 165 points

    Hi,

    I'm learning about the use of GPMC for simple transfer of 16-bit word to/from the FPGA.

    Can you share with me your driver and simple test application for the similar setup so that I can learn from it?

    Many thanks in adv.

    James Ang.

  • 0
    Prodigy 40 points

    The solution ended up being that the driver that implements the mmap file operation was not explicitly setting the virtual memory pages to non-cached using the pgprot_noncached call. Once this change was made we stopped seeing any caching/prefetching behavior.