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AM5749: Disabling unused EMIF2

Stephen Williams
Prodigy 20 points

Part Number: AM5749

We are developing a bare-metal application on the AM5749 processor. As we are using ECC memory, and ECC memory is only supported on the EMIF1 interface, the EMIF2 interface is unused. We wish to disable the EMIF2 module.

We have set CM_EMIF_EMIF2_CLKCTRL -> MODULEMODE to 0x0 (module disabled by software).

TRM "Table 3.241. CD_EMIF Modules Slave CLock-Management Modes and Control" states that disabling of the EMIF2 module via this register is supported, however following setting of MODULEMODE to 0x0 we see that CM_EMIF_EMIF2_CLKCTRL -> IDLEST remains at 0x1 (module performing transition) rather than moving to 0x3 (module disabled) as expected.

Please advise as to the correct procedure for disabling EMIF2.

Kind regards,
Stephen

  • 0
    TI__Mastermind 40036 points

    Hello Stephen,

    Looking into your question, will respond by tomorrow at the latest.

    -Josue

  • 0 in reply to Josue Zamitiz-Ayala
    TI__Mastermind 40036 points

     

    From my investigation, I am not sure that disabling EMIF 2 completely is possible. First off,

    Both EMIF modules are on the same Power domain:

    Secondly, there are also other dependencies like you have to ensure the dmm lisa maps are not accessing EMIF 2 and the CM_EMIF_CLKSTCTRL MODULEMODE is also set to HW_AUTO (0x3), which will automatically gate the clocks when the module is not in use.

    Hope this gives you some direction.

    Best,

    Josue

  • 0 in reply to Josue Zamitiz-Ayala
    Prodigy 20 points

    The fact that EMIF2 is part of an "always on" power domain shouldn't be relevant, I see no restriction on disabling modules connected to always on power domains and we have been able to disable many such modules.

    As suggested our DMM LISA maps are for EMIF1 only.

    It does appear that EMIF2 cannot be disabled whilst EMIF1 is enabled. Looking closer at the clock tree I see that the same functional clocks are routed to both EMIF devices, i.e. you cannot gate the EMIF2 clocks whilst having the EMIF1 clocks running.

    Looks like we'll need to leave EMIF2 enabled but isolated via the DMM LISA mappings.

    Thanks for your help in this matter.