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Original question:

SK-AM62A-LP: Specifying _c_int00_secure as the entry_point results in a runtime error.

AM62D-Q1: About Cache and MMU WT/WB settings

O.H
Mastermind 7240 points

Part Number: AM62D-Q1
Other Parts Discussed in Thread: SYSCONFIG

Hi experts,

This is a question related to this thread.
 
Q: When selecting the L1D cache setting of AM62D or AM62A with CacheP_enableWT/CacheP_enableWB, should the MMU Armv8 cache policy setting be changed to match WT/WB?
In the measurement comparing WT and WB, both the L2SRAM area and DDR area where programs and data are deployed use MAIR7.
(In sysconfig: Attr Index 7: Normal outer and inner write-back cacheable non-transient memory)
It would be helpful if you could tell me the settings used in your company's tests.
 
Bet regards,
O.H
  • 0
    TI__Genius 14440 points

    Hi O.H,

    O.H said:
    Q: When selecting the L1D cache setting of AM62D or AM62A with CacheP_enableWT/CacheP_enableWB, should the MMU Armv8 cache policy setting be changed to match WT/WB?
    In the measurement comparing WT and WB, both the L2SRAM area and DDR area where programs and data are deployed use MAIR7.
    (In sysconfig: Attr Index 7: Normal outer and inner write-back cacheable non-transient memory)
    It would be helpful if you could tell me the settings used in your company's tests.

    We also use MAIR7 as you can see in the examples present in the SDK. If L1D is configured for Write-Through mode in L1DCFG, L1D is set for Write-Through mode, regardless of MMU table entry.


    Thanks,
    Shreyansh

  • 0 in reply to Shreyansh Anand
    Mastermind 7240 points

    Hi Shreyansh,

    Thank you for your support.

    If the L1DCFG setting is WT, I understand that it is acceptable for the MMU(L2, DDR) to use MAIR7 (WB).
    According to the customer's test results, when L1DCFG was set to WT and matched to MAIR6 (WT), there was a tenfold increase in cycles compared to MAIR7 (WB). [4000→40000]
    Best regards,
    O.H