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VPBE's VCLK frequency?

Hi~ 

I using 6437DSP to create YCC8 digital out. I confused about how to calculate the VCLK's frequency.

1. I set PLLC2 output 81Mhz for VPSS, and then I get 40.6Mhz from VCLK. Is that right?

2. if Q1 is right. May I set VENC_CLK to 54Mz and let VCLK output the same frequency?

 

  • Sorry for the trouble, but the letters in front of the device number indicate the device family. The DM6437 is supported in the DM64x Forum. We will have this question moved from this C64x Single Core Forum to the correct place. There will be more people watching that forum who may be able to help you.

    For the clock frequencies you are asking about, have you located block diagrams in the datasheet or User Guides that show the method of generating clocks. These are usually supplied to help you determine things like this.

    You may want to be clear which frequency you want VCLK to be the same as.

    Regards,
    RandyP

  • I want output 720x480 image. the interface of output is YCC8 digital and the VCLK need up to 54Mhz or more. 

    I select the frequency source from SYSCLK2 of PLLC2.

    first the SYSCLK2 is 54Mhz.

    VPSS clock source.

    VPSS_CLK_CTRL       = 0x00000019;  

    the DCLK set:

    VPBE_VENC_DCLKCTL= 0x00000800;
    VPBE_VENC_DCLKPTN0 = 0x1;
    VPBE_VENC_DCLKPTN1 = 0x0;
    VPBE_VENC_DCLKPTN2 = 0x0;
    VPBE_VENC_DCLKPTN3 = 0x0;
    VPBE_VENC_DCLKPTN0A = 0x0;
    VPBE_VENC_DCLKPTN1A = 0x0;
    VPBE_VENC_DCLKPTN2A = 0x0;
    VPBE_VENC_DCLKPTN3A = 0x0;

    I detect the pin of the VCLK output frequency is not 54MHz. The max frequency is 27Mhz. 

    So I up the SYSCLK2 frequency to be 108Mhz. VLCK is right 54MHz.

    But the wave of the VCLK is not Square wave. It's like sine wave. So I can't receive the right Image. 

    Dose the register have wrong?

    If the setting is right, why?

  • sorry it's my wrong.

    the hardware detected wrong pin.