AISgen pre-div and running C6747 at 372 MHz

Hi,

Is there any specific reason you want to set PREDIV to 2 and POSTDIV to 1?

PREDIV = 1, PLLM = 31, POSTDIV = 2 can give you 372 MHz CPU clock.

Urmil,

Yes because PLLM=31 gives 744 MHz VCO and I think this is above the maximum allowed at 600 MHz?  Correct me if I am wrong.

Thanks,

Fawad

You are correct. The boot loader / AISgen tool do not support configuring PREDIV.

The only option I can suggest for now is to boot the device initially at a lower speed and then reconfigure PLL to higher speed.

Urmil,

On another post

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/160778.aspx

There is talk of using the AIS_Set command to set the DIV register on a C6748.  Can it be done with the C6747?

There is already a AIS_SET in my default AISgen.ini (its for the C6747/OMAP-L137 EVAL board)

; DIV4p5
[AIS_Set]
TYPE    = 0x00020004
ADDRESS = 0x01C14188
DATA    = 5
SLEEP   = 0

Thanks,

Fawad

Hi Fawad,

AIS_SET command is available for C6747 as well but PLL configuration is a series of commands that involves writing to PLL registers in a logical sequence and waiting for a given amount of clocks after each write for PLL to lock. Writing to PREDIV asynchronously using AIS_SET may not be a good idea.

On the other hand, PLL on C6748 is different and the ROM bootloader in latest version of device does support setting PREDIV.

I still recommend a 2-stage boot process where the first stage gets loaded by ROM boot loader at default speed (300 MHz) and then it reconfigures PLL to higher speed before loading & executing second stage (application).

Urmil.

Well I was able to use AIS_SET to set pre-div to 2 and can boot up the DSP at 372 MHz.  So far I have not seen any issue.  I did not want to go to a 2-stage boot process as I am booting the DSP from UART and it is already pretty slow (UART boot is limited to 115kbaud).

I used the following AIS_SET command

; Pre-div divide by 2
[AIS_Set]
TYPE    = 0x00020004
ADDRESS = 0x01C11114
DATA    = 0x00008001
SLEEP   = 0

Thanks,

Fawad

Hi Fawad,

That's a good news!

Did you set it before or after PLL initialization?

May I request you to share portion of your .ini file including PLL configuration (and any other related setup) for the benefit of other users?

Urmil,

I set the Pre-div before the PLL initialization.  As show below in the AISgen.ini file

; Pre-div divide by 2
[AIS_Set]
TYPE    = 0x00020004
ADDRESS = 0x01C11114
DATA    = 0x00008001
SLEEP   = 0

[PLLANDCLOCKCONFIG]
PLLCFG0 = 0x1E000202
PLLCFG1 = 0x0005018C
PERIPHCLKCFG = 0x0001007C

However note the PLLANDCLOCKCONFIG has also changed

for the 300 MHz the settings are

[PLLANDCLOCKCONFIG]
PLLCFG0 = 0x18010202
PLLCFG1 = 0x000501B9
PERIPHCLKCFG = 0x00010064

; DIV4p5
[AIS_Set]
TYPE    = 0x00020004
ADDRESS = 0x01C14188
DATA    = 5
SLEEP   = 0

Changes from  300 MHz (reference Design)  to 372 MHz C6747 (Note the crystal in both cases is 24 MHz).

1.  Run AISgen for D800K003.  To generate the correct PLLANDCLOCKCONFIG in the 372 MHz case I had to set the Clock to 12 MHz, Multiplier to 31 and POSTDIV to 1 and also disable the 4.5 divider for EMIFB.  This generates the AISgen.ini

2.  Edit AISgen.ini and add the pre-div divide by 2 part before the PLLANDCLOCKCONFIG by using any text editor.

3.  Run HexAIS_OMAP-L137.exe and use this new AISgen.ini file.

4.  SDRAM will now run at 120 MHz (rather than 133 MHz in the reference design).  But after looking at how to calculate all the SDRAM settings I did not see any reason to change any of the settings.  But the SDRAM settings could be improved by a few clocks cycles for some of the settings.

I confirmed with CCS debug that the registers in the DSP are correct.  I got approx 22% improvement in the performance of the DSP. which is close to the theoretical 25% due to clock speed increase.  Most of my critical code is in internal RAM so I am not too affected by the SDRAM running 9% slower.

Also if you use DSP/BIOS and PSP you have to modify soc_C6747.h as follows

#define CSL_SYSCLK_1_FREQ                   (372000000)              // was 300000000

Thanks,

Fawad

The SDRAM is running at 124 MHz and not at 120 MHz.

Thanks, Fawad. This is very useful.