Part Number: TDA4AH-Q1
While running at cold our clock begins about -150 ppm out from the nominal frequency and takes about 30s to come in range (+/- 100ppm) after the SOC is released from reset. While evaluting ways to fix this issue, we wondered if it was an issue to be running the clock slow for the first 30s? This spec is taken from: 
We are not using RMII or RGMII. But we are using SGMII. The arguement is that since we are running slower there should be better internal timing characteristics. Is this true? I could also see an arguement where DDR and eMMC calibration happen at this lower frequency and then we see issues during normal operation?
Is it possible to run the clock slower than the nominal frequency just after the SOC is released from reset?
