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TDA4VE-Q1: J721S2: PWM Configurations andiInterrupt callback

Veerahema Kalaiselvan
Intellectual 361 points

Part Number: TDA4VE-Q1

HI All,

I am facing an issue with the interrupt. I am not receiving the interrupt callback after starting the PWM. I am using below IRQ and BASE address Please confirm the below details are correct for MCU2_0

#define EPWM_BASE_ADDR   (CSL_EPWM1_EPWM_BASE)
#define EPWM_IRQ_NUM     (CSLR_R5FSS0_CORE0_INTR_EPWM1_EPWM_ETINT_0) //R5F 2_0

image.png

Please find the below modifications.

GPIO configurations:

const uint32_t CSL_GPIO0_PIN_62 = 62;

const uint32_t P24_padconfig_addr = 0x0011C0F8;

volatile uint32_t * GPIO_P24 = (uint32_t*) (P24_padconfig_addr);

 *GPIO_P24 = 0X10004;

    GPIOSetDirMode_v0(CSL_GPIO0_BASE, CSL_GPIO0_PIN_62, GPIO_DIRECTION_OUTPUT);  //TDAS_EPWM1_B_DES_SVC_960_GPIO_0_FSYNC

    GPIOPinWrite_v0(CSL_GPIO0_BASE, CSL_GPIO0_PIN_62, GPIO_PIN_HIGH);

    Board_STATUS boardEnST = Board_moduleClockEnable(TISCI_DEV_EPWM2);

    int32_t status = Sciclient_pmSetModuleState(   TISCI_DEV_EPWM2,
                                           TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
                                           TISCI_MSG_FLAG_AOP |TISCI_MSG_FLAG_DEVICE_RESET_ISO,
                                           SCICLIENT_SERVICE_WAIT_FOREVER);

--------------------------------------------------------------------------------------------------

PWM configurations1

  1. Unlock all the MMR registers.
  2. Init all registers to default value
  3. CSL_epwmTbTimebaseClkCfg(EPWM_BASE_ADDR, tbClk, SOC_EPWM_MODULE_FREQ);
  4. CSL_epwmTbPwmFreqCfg(EPWM_BASE_ADDR, EPWM_TB_CLK_HZ_U32, periodCounts,
                        CSL_EPWM_TB_COUNTER_DIR_STOP, CSL_EPWM_SHADOW_REG_CTRL_ENABLE);
  5. CSL_epwmTbSetEmulationMode(EPWM_BASE_ADDR, EPWM_TB_EMU_MODE_FREE_RUN);
  6. CSL_epwmCounterComparatorCfg(EPWM_BASE_ADDR, CSL_EPWM_CC_CMP_B, pulseCounts, CSL_EPWM_SHADOW_REG_CTRL_ENABLE, CSL_EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE);
  7. CSL_epwmAqActionOnOutputCfg(EPWM_BASE_ADDR, CSL_EPWM_OUTPUT_CH_B, &AqActCfg);

Enable Interrupt:

8.  CSL_epwmEtIntrClear(EPWM_BASE_ADDR); 

9. CSL_epwmEtIntrCfg(EPWM_BASE_ADDR, CSL_EPWM_ET_INTR_EVT_CNT_EQ_ZRO,                              CSL_EPWM_ET_INTR_PERIOD_FIRST_EVT);

10. CSL_epwmEtIntrEnable(EPWM_BASE_ADDR);

11. HwiP_clearInterrupt(EPWM_IRQ_NUM);

12.  HwiP_Params_init(&hwiParams);

13.   hwiParams.priority  = 1; 
        hwiParams.enableIntr = true;

       handle = HwiP_create(EPWM_IRQ_NUM, fsyncPwmIRQ, &hwiParams);

14.  HwiP_enableInterrupt(EPWM_IRQ_NUM);

start the FSYNC

 CSL_epwmTbPwmFreqCfg(EPWM_BASE_ADDR,  EPWM_TB_CLK_HZ_U32, m_CurfsyncPeriod_ticks,
                     CSL_EPWM_TB_COUNTER_DIR_UP,CSL_EPWM_SHADOW_REG_CTRL_ENABLE);

Above configurations i am using . Please let me know anything else i am missing.

Thanks & Regards,

Veerahema