TMS320C6655: SRIO Link Interruption with FPGA Periodically

Kevin Peng

Part Number: TMS320C6655

Hi TI Experts,

Customer is working on C6655, and found a problem in SRIO part.

When they conduct the PRBS testing with the FPGA, and it was discovered that the current SRIO physical layer experiences a link interruption approximately every 40 seconds periodically. This phenomenon was detected on both the FPGA and DSP sides. However, after the link down happens every 40 seconds, the link can quickly self-recover, and this has no noticeable impact on the applications.

This happens on all their developed boards.

Customer has SOP C6652, C67 many years ago, so they have experience in C66 family. Although it is the first time they build C6655 board, but we believe it should not be much difference with C6652 which they have SOP for years and quite stable. The only thing is, SRIO connecting with FPGA is the new feature they first time try on C66 family.

Customer hopes to have some suggestions on how to debug with this problem.

Could you please have some suggestions?

Thanks,

Kevin

4 months ago

0 Betsy Varughese 4 months ago

TI__Expert 7090 points

Hi Kevin,

Have you tried replacing PRBS with normal SRIO traffic (packet‑based communication) to check whether the issue still persists?

I noticed an errata issue reported as “Corruption of Control Characters in SRIO Line Loopback Mode”, along with a corresponding workaround described in Advisory 7.

Could you please refer to the same and let us know if it is relevant in this case?

For reference, please find below a link to a previous E2E post that addresses SRIO-related queries:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/170264/srio-help-for-beginners-c6678-and-srio-switch?

Regards,

Betsy Varughese

0 Kevin Peng 3 months ago in reply to Betsy Varughese

TI__Expert 4998 points

Hi Betsy,

We have narrow down the issue finally!

We've made a new discovery. Under the current configuration of 200 MHz kernel clock and 125 MHz SRIO reference clock, we observed periodic disconnections on the DSP side. However, after switching to 100 MHz kernel clock and 250 MHz SRIO reference clock configuration, the issue disappeared. In the software, only the multiplication factor was modified, while the kernel continues to operate at 1 GHz and SRIO works in 5G mode.

What could be causing this situation? Is it due to issues with the external clock itself, an unreasonable clock frequency, or insufficient PLL parameter configuration?

Thanks,

Kevin

0 Betsy Varughese 3 months ago in reply to Kevin Peng

TI__Expert 7090 points

Hi Kevin,

Could you please share the current PLL configuration details?

Regards,

Betsy Varughese

+1 Betsy Varughese 3 months ago in reply to Betsy Varughese

TI__Expert 7090 points

Hi Kevin,

Could you please refer Section 2.3.1 SerDes Macro and its Configurations & Section 3.2.2: SerDes Macro Configuration Register Serial RapidIO (SRIO) for KeyStone Devices User's Guide, to ensure everything is configured correctly.

The Serial Rapid I/O Boot Device Configuration as follows. The reference clock supported is 156.25 MHz, 250 MHz & 312.5 MHz.

Regards,

Betsy Varughese

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TMS320C6655: SRIO Link Interruption with FPGA Periodically