AM335X IBIS - DDRx section

Hi!

The meaning of the  [number]* RExt values can be found in the IBIS model.

The driver strength can be set in I[2:0] section of the ddr_cmd0_ioctrl and ddr_cmd1_ioctrl and ddr_cmd2_ioctrl and ddr_data1_ioctrl and ddr_data0_ioctrl registers of the control module.

The slew rate of the signals can be set in the same registers in the SR[1:0] section.

I have not found any information about the ODT settings (Half Thevenin, FULLTERM, Pull-down, Pull-up/down off). In the SDRAM_CONFIG register (EMIF4D register set) you can set the ODT remination values with reg_ddr_term[2:0].

But I don't know how to connect these with the IBIS model.
Does anyone have more information?

Best Regards,

Balazs Ancsa 

Hi Balazs, 

You are right to setting selection of drive strengths.But there is complexity input termination settings still. I have asked directly TI, but I

did not received satisfiying answer. If any answers come back to me, I will share it on this page.

Best Regards,

FERHAT 

Hi!

I could figure out the settings of the DDR controller (thanks for measurements)

• The driver strength can be set in I[2:0] section of the ddr_cmd0_ioctrl, ddr_cmd1_ioctrl, ddr_cmd2_ioctrl, ddr_data0_ioctrl and ddr_data1_ioctrl registers of the control module.

setting	driver strength	I[2:0]
1.60*RExt	5mA	000
1.33*RExt	6mA	001
1.14*RExt	7mA	010
1.00*RExt	8mA	011
0.88*RExt	9mA	100
0.80*RExt	10mA	101
0.73*RExt	11mA	110
0.67*RExt	12mA	111

• The slew rate of the signals can be set in the same registers in the SR[1:0] section.

slew rate	SR[1:0]
slowest	11
slow	01
fast	10
fastest	00

• The ODT settings can be set in the DDR_PHY_CTRL_1 and DDR_PHY_CTRL_1_SHADOW register in the reg_hpy_rd_local_odt[1:0] section.

ODT	reg_phy_rd_local_odt[1:0]
Disabled	00
Disabled	01
Full	10
Half	11

• The memory settings can be set in the EMIF_SDRAM_CONFIG register (this will be transfered to the DDR memory during initialization)
  • ODT settings in reg_ddr_term[1:0] section

ODT	reg_ddr_term[1:0]
Disabled	00
75 Ohm	01
150 Ohm	10
50 Ohm	11

• • Drive settings in reg_sdram_drive[0] section.

ODT	reg_sdram_drive[0]
Normal	0
Reduced	1

If I am right, the reference manual has a mistake in the DDR_PHY_CTRL_1 register description.

It says for the reg_hpy_rd_local_odt[1:0] bits that 0b01 is full thevenin ODT and 0b10 is disabled ODT.
I have tried this settings it seems that 0b01 is the disabled ODT and 0b10 is full thevenin ODT.

Could somebody verify this?

Best Regards,
Balázs 

Yes, Balazs, you are correct 0x01 is disabled, and 0x10 is full thevenin ODT.  Those will be fixed in the next TRM release. 

Regard,s

James

I'll add one additional piece of info to this already useful thread!  There are some models like this:

[model]         Model_714

|     Sub model VREF_NOTERM_PUPD_OFF_5PER_1P8

[model]         Model_726

|     Sub model LVCMOS_PUPD_OFF_5PER_1P8

The "VREF" models refer to DDR2/DDR3 while the "LVCMOS" models refer to LPDDR.  This corresponds to the programming of ddr_io_ctrl.mddr_sel in the TRM (i.e. 0 for DDR2/DDR3 and 1 for LPDDR).

As we see it, in order to actually do a simulation we will have to:

                1) read back the configuration registers over the JTAG interface.

                2) parse the data comparing register addresses to data sheet to determine settings

                3) coordinate our findings with our Hyperlynx guy to assist him in correctly configuring his simulation tools to our specific application.

All this is labor intensive and prone to errors.

Has anyone created a PC application that will read back the appropriate data, parse it, and generate an “application” specific IBIS model or creation a file that we can send to TI for “application” specific IBIS model creation.

Blake -- I would envision the process being the other way around, i.e. the hardware guy does the simulation and tells the software guy how he's supposed to configure the DDR.

On a related note, I've created this wiki page to try and bring all this info together in one place:

http://processors.wiki.ti.com/index.php/How_to_use_the_AM335x_IBIS_Models

If nothing else, both the simulation/hardware engineer and the software engineer can both read the article to understand how they are expected to coordinate the activity.