• State
  • Locked Locked
  • Replies 20 replies
  • Subscribers 100 subscribers
  • Views 360 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VEN-Q1: Using a four-channel 3M YUV camera will result in a black screen during high and low temperature stress testing.

xie jc
Expert 2440 points

Part Number: TDA4VEN-Q1

Hi TI experts,

  When we were performing high and low temperature durability stress tests, we found that after testing for several hours, the entry's capture would have zero frame rate 100% of the time. At this point, the deserializer does have MIPI output, so we suspect that there is an issue with csirx. The MCU2_0 is also running normally at this time, but there is simply no frame rate. Previously, our projects with entry used 1M cameras, and this is the first time we are doing this kind of stress test with a 3M camera. I would like to ask if you have encountered a similar problem on your side? How should this issue be troubleshooted and resolved?

Thanks!

  • 0
    TI__Guru**** 501245 points

    Hi xie jc,

    Which sdk release are you using? Have you disable LDC WDG timer in this run? If VPAC or any other component gets stalled due to some reason, then entire pipeline will get stalled, so we need to see which component is stalled. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Expert 2440 points

    I am using the 10.1 SDK. At first, I tested using LDC. Later, to rule out LDC's impact, I removed all VPAC nodes and kept only the capture, then output through the GPU, but the problem still occurs

  • 0 in reply to xie jc
    TI__Guru**** 501245 points

    hi xie jc,

    Do you have performance statistics to see if capture is running out of buffers and its just dropping all frames? Also are you using SafeRTOS on any of the cores? 

    Also what is "durability stress tests"? Are you doing on/off during this test or reloading the cores during this test?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Expert 2440 points

    1. No, but this issue does not occur at room temperature; it only appears at high and low temperatures, so the probability of buffer exhaustion caused by the application side is low.
    2. We currently use Secure Boot. What do you mean by SafeRTOS? Is it functionally safe? We have not enabled functional safety.
    3. This durability stress test means that the board is powered on only once without rebooting, gradually increasing the ambient temperature to around 100 degrees, and then lowering the temperature down to -40 degrees. The issue can appear in about four to five hours.

  • 0 in reply to xie jc
    TI__Guru**** 501245 points

    Hi xie jc,

    Can we please get the performance statistics when this issue comes? 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    TI__Genius 11151 points

    Hi xie jc,

      Could you please use the script to dump the register, It would  help us check  the status when issue happened. Thanks.

    /cfs-file/__key/communityserver-discussions-components-files/791/TDA4_5F00_Entry_5F00_CSIRX_5F00_IF1.tar.xz

    Linjun

  • 0 in reply to Linjun Meng
    Expert 2440 points

    Fullscreen csirx_ok.txt Download 
    ==================== CSI RX Register Read ====================

=== CSI RX IF1 CP INTD CFG (Base: 0x30120000) ===

0x30120000 = 0x6690a200 CP_INTD__INTD_CFG__INTD_CFG_REVISION
0x30120010 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_eoi_reg
0x30120014 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg
0x30120100 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_0
0x30120104 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_0
0x30120300 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_0
0x30120304 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_0
0x30120500 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_0
0x30120504 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_0
0x30120700 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_0
0x30120704 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_0
0x30120a80 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level
0x30120a84 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse

=== CSI RX IF1 RX SHIM VBUSP MMR CSI2RXIF (Base: 0x30122000) ===

0x30122000 = 0x64700101 RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_csirx_id
0x30122008 = 0x00000000 RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp0
0x3012200c = 0x00000000 RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp1
0x30122010 = 0x00000e01 RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_cntl

=== CSI RX IF1 VBUS2APB WRAP VBUSP APB CSI2RX (Base: 0x30121000) ===

0x30121000 = 0x8421164c VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_device_config
0x30121004 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_soft_reset
0x30121008 = 0x43210410 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_static_cfg
0x30121010 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_bypass_cfg
0x30121018 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs
0x3012101c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs_mask_cfg
0x30121020 = 0x00000022 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs
0x30121024 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs_mask_cfg
0x30121028 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs
0x3012102c = 0x000f03b1 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs_mask_cfg
0x30121040 = 0x0001f01f VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_lane_control
0x30121048 = 0x00222206 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_status
0x3012104c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_status_irq
0x30121050 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_irq_mask_cfg
0x30121060 = 0x10000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_integration_debug
0x30121074 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_debug
0x30121080 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_test_generic
0x30121104 = 0x80000133 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_status
0x30121108 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_data_cfg
0x3012110c = 0x00000100 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_cfg
0x30121110 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_ctrl
0x30121114 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_frame
0x30121118 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_lb
0x3012111c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_timer
0x30121120 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_cfg
0x30121124 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_ctrl
0x30121128 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fifo_fill_lvl
0x30121204 = 0x00000100 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_status
0x30121208 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_data_cfg
0x3012120c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_cfg
0x30121210 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_ctrl
0x30121214 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_frame
0x30121218 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_lb
0x3012121c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_timer
0x30121220 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_cfg
0x30121224 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_ctrl
0x30121228 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fifo_fill_lvl
0x30121304 = 0x00000100 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_status
0x30121308 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_data_cfg
0x3012130c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_cfg
0x30121310 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_ctrl
0x30121314 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_frame
0x30121318 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_lb
0x3012131c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_timer
0x30121320 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_cfg
0x30121324 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_ctrl
0x30121328 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fifo_fill_lvl
0x30121404 = 0x00000100 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_status
0x30121408 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_data_cfg
0x3012140c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_cfg
0x30121410 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_ctrl
0x30121414 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_frame
0x30121418 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_lb
0x3012141c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_timer
0x30121420 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_cfg
0x30121424 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_ctrl
0x30121428 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fifo_fill_lvl
0x30121920 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_corr_fault_status
0x30121924 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_uncorr_fault_status
0x30121930 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_ctrl
0x30121934 = 0x00000001 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_mask
0x30121938 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_status
0x30121940 = 0x00003fff VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_mask
0x30121944 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_status
0x30121ffc = 0x50220200 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_id_prod_ver

==================== Read Complete ====================
    Fullscreen csirx_error.txt Download 
    ==================== CSI RX Register Read ====================

=== CSI RX IF1 CP INTD CFG (Base: 0x30120000) ===

0x30120000 = 0x6690a200 CP_INTD__INTD_CFG__INTD_CFG_REVISION
0x30120010 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_eoi_reg
0x30120014 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg
0x30120100 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_0
0x30120104 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_0
0x30120300 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_0
0x30120304 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_0
0x30120500 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_0
0x30120504 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_0
0x30120700 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_0
0x30120704 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_0
0x30120a80 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level
0x30120a84 = 0x00000000 CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse

=== CSI RX IF1 RX SHIM VBUSP MMR CSI2RXIF (Base: 0x30122000) ===

0x30122000 = 0x64700101 RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_csirx_id
0x30122008 = 0x00000000 RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp0
0x3012200c = 0x00000000 RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp1
0x30122010 = 0x00000e01 RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_cntl

=== CSI RX IF1 VBUS2APB WRAP VBUSP APB CSI2RX (Base: 0x30121000) ===

0x30121000 = 0x8421164c VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_device_config
0x30121004 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_soft_reset
0x30121008 = 0x43210410 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_static_cfg
0x30121010 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_bypass_cfg
0x30121018 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs
0x3012101c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs_mask_cfg
0x30121020 = 0x00000022 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs
0x30121024 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs_mask_cfg
0x30121028 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs
0x3012102c = 0x000f03b1 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs_mask_cfg
0x30121040 = 0x0001f01f VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_lane_control
0x30121048 = 0x00333306 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_status
0x3012104c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_status_irq
0x30121050 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_irq_mask_cfg
0x30121060 = 0x10000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_integration_debug
0x30121074 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_debug
0x30121080 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_test_generic
0x30121104 = 0x80000133 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_status
0x30121108 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_data_cfg
0x3012110c = 0x00000100 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_cfg
0x30121110 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_ctrl
0x30121114 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_frame
0x30121118 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_lb
0x3012111c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_timer
0x30121120 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_cfg
0x30121124 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_ctrl
0x30121128 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fifo_fill_lvl
0x30121204 = 0x00000100 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_status
0x30121208 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_data_cfg
0x3012120c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_cfg
0x30121210 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_ctrl
0x30121214 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_frame
0x30121218 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_lb
0x3012121c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_timer
0x30121220 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_cfg
0x30121224 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_ctrl
0x30121228 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fifo_fill_lvl
0x30121304 = 0x00000100 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_status
0x30121308 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_data_cfg
0x3012130c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_cfg
0x30121310 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_ctrl
0x30121314 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_frame
0x30121318 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_lb
0x3012131c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_timer
0x30121320 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_cfg
0x30121324 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_ctrl
0x30121328 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fifo_fill_lvl
0x30121404 = 0x00000100 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_status
0x30121408 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_data_cfg
0x3012140c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_cfg
0x30121410 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_ctrl
0x30121414 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_frame
0x30121418 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_lb
0x3012141c = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_timer
0x30121420 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_cfg
0x30121424 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_ctrl
0x30121428 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fifo_fill_lvl
0x30121920 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_corr_fault_status
0x30121924 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_uncorr_fault_status
0x30121930 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_ctrl
0x30121934 = 0x00000001 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_mask
0x30121938 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_status
0x30121940 = 0x00003fff VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_mask
0x30121944 = 0x00000000 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_status
0x30121ffc = 0x50220200 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_id_prod_ver

==================== Read Complete ====================

    As shown in the attachment, I have captured the registers in both faulty and normal states. After checking, one register is different.
    Normal: 0x30121048 = 0x00222206 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_status
    Abnormal: 0x30121048 = 0x00333306 VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_status

  • 0 in reply to Brijesh Jadav
    Expert 2440 points

    When the problem occurs, the program is in a blocked state and cannot print out complete information.

  • 0 in reply to xie jc
    TI__Guru**** 501245 points

    hi xie jc,

    if possible, can you please connect to R5F, load the symbols and put breakpoint on capture dma callback to see if the capture is still working? this callback API is CsirxDrv_udmaCQEventCb. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    TI__Mastermind 20011 points

    Dear Brijesh.

    update from customer, they found CSIRX receiving is good, the problem comes from C7x when it does data format convert. 

    They will continue to check that and go back to update the ticket if need your help.

    thanks a lot!

    yong

  • 0 in reply to Yong Zhang
    Expert 2440 points

    I connected to CCS when the problem occurred and captured the states of MCU2_0 and C7X. Could you please take a look at what the problem is?

  • 0 in reply to xie jc
    TI__Guru**** 501245 points

    Hi xie jc,

    Does it mean mcu2_0 is crashed? In one of the screen shot, i see it is in undefined handler, is it exception handler? Capture might still be running in this case, but due to exception, mcu2_0 might have stopped. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Expert 2440 points

    We are now sending the images directly captured from CAPTURE to the GPU for stitching and display, and there have been no cases of C7x or MCU20 crashing. However, a new problem has appeared: the GPU has crashed. Please take another look.7750.kernel.log

  • 0 in reply to xie jc
    TI__Guru**** 501245 points

    Hi xie jc,

    i will not be able to help in GPU case, i will request   to help you here.

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Expert 2440 points

    Okay, please analyze it as soon as possible.

  • 0 in reply to xie jc
    TI__Mastermind 21460 points

    Hello, 

    Could you run these commands and provide the generated log file.

    1. Before running the application, run the following command:
      `pvrdebug -loggroups main,mts,hwr`
    2. After experiencing an error in execution, run the following command: `pvrlogdump`. This will generate a file that can be shared on the E2E ticket for further analysis.

    Thanks,
    Sarabesh S.

  • 0 in reply to Sarabesh Srinivasan
    Expert 2440 points

    The issue has reproduced. The log is as follows:

    pvrlogdump_j722s-evm_0001040452.txt

  • 0 in reply to xie jc
    TI__Mastermind 21460 points

    Hello, 

    Thanks for sharing the debug log. I will take a look and get back to you with my findings/next steps within 1-2 days. 

    BR,
    Sarabesh S.e

  • 0 in reply to Sarabesh Srinivasan
    Expert 2440 points

    Is there any progress?

  • 0 in reply to xie jc
    TI__Mastermind 21460 points

    Hello, 

    Thanks for sharing the pvrlogdump. After analysis, the GPU seems to have recovered from the faults but during those faults the application failed. I suspect the issue is in the mv_avm application since the GPU tried to access a memory address that was empty. 

    Is your application using OpenGL or Vulkan?

    Can you check if your application is releasing the GPU buffers before the GPU job is complete? If using OpenGL ES or Vulkan, verify that glFinish()/vkWaitForFences() is called before releasing input buffers.

    If this is not the case, do you have any temperature data that we can correlate with when the HWR occur?

    Thank you,
    Sarabesh S.