This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDR3 init on custom board

Hi, all!

I have custom board based on DM816x EVM (rev. G). On the module located two DDR3 16-bit (MT41J128M8JE-125) connected to EMIF1.

I modified  DM816x.gel from PSP to use only EMIF1 and 400 MHz. Than I make doall() function from GEL script it print in CCS console:

CortexA8: Output: 	Device type is GP 
CortexA8: Output: DM816x Main PLL Init is in Progress, Please wait .....
CortexA8: Output: DM816x Main PLL Init is Done .....
CortexA8: Output: DM816x DDR PLL Init is in Progress for 400 MHz DDR Clock, Please wait .....
CortexA8: Output: DM816x DDR PLL Init is Done .....
CortexA8: Output: DM816x DDR2/3 PRCM Init is in progress .....
CortexA8: Output: DM816x DDR2/3 PRCM Init is Done .....
CortexA8: Output: Initializing EMIF1 .....
CortexA8: Output: DDR3 SWLEVELING DONE FOR EMIF1
CortexA8: Output: DM816x EMIF Init is Done @ 400 MHz Clock Rate.....
CortexA8: Output: PRCM for OCMCRAM0/1 Initialization in Progress

If I try to load program (nand-flash-writer.out - need to burn u-boot image in NAND) I have some errors:

CortexA8: File Loader: Data verification failed at address 0xC0100000 Please verify target memory and memory map.
CortexA8: Unable to terminate memory download: NULL buffer pointer at 0x3a9f
CortexA8: GEL: File: D:\ccs_config\nand-flash-writer\NETRA\Debug\nand-flash-writer.out: a data verification error occurred, file load failed.
Any modifications of SDRCR fields do not help to me. 
Please say how I can:
- check DDR3 memory?
- set correct DDR3 parameters.
- burn u-boot image on NAND or SPI.
Thank you.
P.S. Sorry, my English is not very well.
  • Hi, All! 

    If I run program DDR3_slave_ratio_search.out from ti.wiki 

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

    and it was download and work.

    
    

    [CortexA8] Enter 0 for EMIF0 & 1 for EMIF1
    1
    [CortexA8] DDR AADR=c0000000
    [CortexA8] Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
    128
    [CortexA8] Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
    40
    [CortexA8] Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
    9f
    [CortexA8] DLL Lock Values at Start  6a,  6b,  6b,  6b
    [CortexA8] ===== Seaching RD DQS GATE =====
    [CortexA8]
    [CortexA8] RD DQS GATE RATIO MAX VALUE=1b5
    [CortexA8] RD DQS GATE RATIO MIN VALUE=aa
    [CortexA8] The RD DQS GATE OPTIMUM VAL=12f
    [CortexA8]
    [CortexA8] ===== Seaching RD DQS =====
    [CortexA8]
    [CortexA8] RD DQS RATIO MAX VALUE=53
    [CortexA8] RD DQS RATIO MIN VALUE=16
    [CortexA8] The RD DQS OPTIMUM VAL=34
    [CortexA8]
    [CortexA8] ===== Seaching WR DQS =====
    [CortexA8]
    [CortexA8] WR DQS RATIO MAX VALUE=ff
    [CortexA8] WR DQS RATIO MIN VALUE=35
    [CortexA8] The WR DQS RATIO OPTIMUM VAL=9a
    [CortexA8]
    [CortexA8] ===== END OF TEST =====

    What differences between DDR3_slave_ratio_search.out and nand-flash-writer.out?