iss video capture problem

Hi Li dong,

Can you increase the vertical blanking from the sensor and try again? It seems that the Resizer is not getting enough time to process between the frames.

Regards

Rajat Sagar

Hi ,

 I have increase the vertical blanking ,but when capture as 12 fps it still work abnormal .

because i use the one-shot mode,  IPIPEIF read  RAW image data from DDR ,then to de IPIPE->RSZ->DDR(YUV),.

when i set the ISP5_BL_MTC_1 IPIPEIF_R as 128,and IPIPEIF_CLKDIV m=3 ,n=5.  the RSZ can output 12 fps, but RSZ_FIFO_IN_BLK_ERR and RSZ_FIFO_OVF bit in ISP5_IRQSTATUS_RAW frequently ,and can not trigger RSZ_INT_DMA interrupt.

but when i set the ISP5_BL_MTC_1 IPIPEIF_R as 256,and IPIPEIF_CLKDIV m=3 ,n=5.  the RSZ output 6 fps, it work normal.

also i do such a test , when i set RSZ_DMA_RZA as 200, it can not  trigger any RSZ_INT_DMA interrupt, set RSZ_DMA_RZA as 0 or 20 ,it works normal.

i doubt whether the ddr bandwidth can effect the RSZ mode,cause it works abnormal?

our ddr used EMIF0 512M ,non-Interlace.

Regards Li dong

Hello Li dong,

The total DDR bandwidth in system will certainly affect the bandwidth seen by resizer dma. If resizer DMA is unable to see enough bandwidth while writing the data to DDR - the overflow bit will be set. There are couple of register settings you can set to increase the DDR write efficiency, example - Burst length = 8x64 bits & write non-post should be enabled, and the resizer, ipipe clocks should be set to maximum in the one-shot mode.

Can you please mail me the register dump from your system environment (mailto:rajat@ti.com). I can review the register and suggest you any improvements if possible.

Some more questions -

1. How is your DDR integration to the emif ports? Are you using both the emif ports for 512M?

2. Interleaving should be enabled - this should give you around 10-15% more ddr efficieny.

3. What is the DDR clock speed you are using? Are you using the default DDR phy timings from the rdk release?

4. What is the ISS M3 clock frequency that you are using?

Regards

Rajat

Hi Rajat,
 
where i can set the Burst length = 8x64 bits & write non-post register bit ?
in the iss trm, i only see these in csi2 ,but i use the Camera Parallel interface.
 
The video data form sensor through ISIF to DDR ,then i control the IPIPEIF one-shot mode to
read the data form DDR to IPIPE &  RSZ , IPIPE & RSZ work at continue mode ,
is it have any hidden trouble? the resizer clk, i set the RSZ_FRACDIV as 0xFFFF works at the maximum.
 
our system use only one emif port, so it only can set as non-interleave,
how can i estimate the ddr maximun bandwidth ,400M * 32/8 *2 =3.2GB/s?
and i estimate our system need 1.2GB/s bandwidth ,
is it can make sure resizer DMA have enough bandwidth to writing the data to DDR?
 
DDR  work at 400M 。 ISS work at 400M  ,M3 is 200M.
 
Also the register dump how can i get it? just the iss register,i can print these use serial port?

Regards

Li dong

HI Li dong,

Which software package are you using for your development? The ISS TRM is an NDA only document - can you check with your local FAE to make it available to you?

Regarding the problem that you are facing,I still suspect that its because of unavailability of DDR BW that the resizer is crashing. Can you increase the DDR frequency to 533 Mhz from the uboot and give it a try? This can only be a temporary experiment - we can discuss how you can further optimize your software to get better ddr utilization at 400Mhz.

Do you have CCS and jtag availability? If so, you can connect to the ISS M3 and dump the register memory for further debug.

Regards

Rajat

Hi Rajat,

I using the centaurus IPNC 0.6 software package,and i have the iss TRM form a FAE in shanghai.

I have tryed to increase the DDR frequency to 533M ,but the problem is still  exist.I have XDS560V2 ,i can  dump the register memory next time.

Today i do a lot of test ,discover that just the A8  execute the memset function also case the ISS RSZ FIFO overflow frequently.

 for example memset(test_buf,0,1024*1024),one time per second. the test_buf is a global array.the FIFO overflow will come soon.

but do

 for(i=0;i<1024*1024;i++)

{

    test_buf[i]=0;

}

replace the memset ,it is work normal.

in our A8 application program,there are a lot of memset operation,the buf len from 1byte to dozens of KB,

 i'd doubt the memset function in A8 exist some hidden trouble ,or when execute may reduce the ddr performance.

can you have a try in your EVM broad?  we only use EMIF0  non-interlace.

Regards

Li dong

Hi Rajat,

I using the centaurus IPNC 0.6 software package,and i have the iss TRM form a FAE in shanghai.

I have tryed to increase the DDR frequency to 533M ,but the problem is still  exist.I have XDS560V2 ,i can  dump the register memory next time.

Today i do a lot of test ,discover that just the A8  execute the memset function also case the ISS RSZ FIFO overflow frequently.

 for example memset(test_buf,0,1024*1024),one time per second. the test_buf is a global array.the FIFO overflow will come soon.

but do

 for(i=0;i<1024*1024;i++)

{

    test_buf[i]=0;

}

replace the memset ,it is work normal.

in our A8 application program,there are a lot of memset operation,the buf len from 1byte to dozens of KB,

 i'd doubt the memset function in A8 exist some hidden trouble ,or when execute may reduce the ddr performance.

can you have a try in your EVM broad?  we only use EMIF0  non-interlace.

Regards

Li dong

Hi Li dong,

My concern is that you are using a very old version of IPNC software. The latest release that we have is IPNC GA 2.0 release package which happened one week back.

I would suggest you to contact the local FAE and get this release asap.

Typically, the resizer buffers should not overflow if DDR bandwidth is available. I suspect that there could be some other issue as well because of which capture is not working correctly. Can you send me a dump of ISIF,  RSZ registers. Also, is it possible for you to try a different resolution like - 1080p or 720p - we have this capture working fine in the releases and can use your experiment to co-relate the data.

I'll review the registers once you send me and send you the feedback, meanwhile I strongly suggest you to pick the latest release.

Best Regards

Rajat

Hi Rajat,

    Because of the Jtag broken,I'sorry that i can't send you the dump of ISIF,  RSZ registers soon,i will do that maybe next week.

   But we may have solve the problem by modify the memset function, and increase the DDR frequence ,i think the reason of this problem is ddr bandwidth,but i don't why we modify the "memset.s " can Improve the problem directly.

  And i have another problem ,about the isif VDINT, i found the ISS TRM say :

ISIF_INT_0: This event is triggered when the VD0 interrupt on line 0 is configured. The VD0 interrupt

can be configured based on the VD position. It is asserted after receiving the number of horizontal

Rajat:

I am experiencing the same issue now.

When one of my applications runs, very frequently it will hang will cause video capture stuck in a short loop. I checked the ISP registers, and found both RSZ_FIFO_IN_BLK_ERR and RSZ_FIFO_OVF are set. If I don't run this application, the video will run for hours without any problem.

I am using RDK2.8, DDR=400Mhz, ISS=400Mhz, 512Mb DDR3 connected to DDR0, all timing values are default.

I see sys_pri.out already set ISS dmm_priority to 0, what else can I do to fix this?

Regards,

Hongfeng,

Which IPNC S/W release are you using?

It seems that you are running into RSZ OVF (DMA overflow) problem, wherein the RSZ stops working due to a internal FIFO overflow. To solve this problem -

1. Migrate to the latest releaes which includes a overflow detect and reset function.

2. If you are using M2M mode then you need to tune the Clock divider ratios so that the read/write speed do not cause DMA overflow.

3. If you are in On the fly mode, then first try reducing the frame rate and check what frame rate is stable enough for you, second you should tune the BW limiter reigisters in RSZ to improve the performance.

Regards

Rajat