Hello,
I am looking into documentation of the Ducati (Dual-Cortex-M3) block on the 'DaVinci-SOCs' (DM81xx and DRA6xx) and trying to understand the configuration of the AMMU.
For the CACHE_MMU registers (ie CACHE_MMU_LARGE_POLY_I) I have problems to understand some of the settings and their meaning.
1. L2_ALLOCATE (L2 allocate policy)
-> 0x0: no writes are allocated --> this probably refers to the 'no-write-allocate' strategy, correct?
-> 0x01: follow sideband --> does this refer then to the 'write-allocate' strategy? What is the meaning of 'follow sideband' here?
2. L2_POSTED (L2 posted policy)
-> posted/ not posted --> What is the meaning of those settings?
3. What do I control by the following register fields? (more details would be helpful)
-> EXCLUSION
-> PRELOAD
-> READ
-> EXECUTE
-> VOLATILE
4. Is there maybe a more detailed description of the AMMU available?
5. When the Ducati block does not have the L2 cache, do I need to set the L2 fields (L2_WR_POLICY, L2_ALLOCATE, L2_POSTED, L2_CACHEABLE) for this AMMU at all? Or is it enough to set the L1 register fields?
Regards,
Heiko
