AM263P4-Q1: SRAM ECC checking

Carwyn Griffiths

Part Number: AM263P4-Q1
Other Parts Discussed in Thread: AM263P4

Hi.

I'm looking to implement ECC memory checks for RAM on the AM263P4 microcontroller to trigger an event on the ESM module. I've noted that there 6 ESM events for SRAM ECC (e.g. sram0_ecc_uncorr_pulse) but can't find any information on how these events are triggered. I've also noted that the soc_eccagg_uncorr_level ESM event looks to be used for RAM ECC monitoring, based on example code in the SDK files.

Could you clarify how ECC checking is set up for RAM, which ESM events are triggered for various fault conditions and any initialisation and fault injection methods used.

Thanks,

Carwyn

22 days ago

0 Kunal Wasnik 21 days ago

TI__Intellectual 1935 points

Hi ,

Nilabh is currently OOO , please expect a delay in response of few days.

0 Nilabh Anand 18 days ago in reply to Kunal Wasnik

TI__Guru 57110 points

The AM263Px uses a hierarchical ECC aggregation architecture with two distinct error paths depending on the memory type. This is the key to understanding the events you're seeing.

Two Error Paths to ESM

1. R5F Core Memories (TCM, Icache, Dcache): These memories output ECC error signals on an internal EVNTBUS. The signals are aggregated in MSS_CTRL registers before being routed to the ESM [1]:

Aggregated Signal	ESM Event	Type
R5SS0_CORE0_CORR_ERRAGG	ESM_LVL_EVENT_47	Level
R5SS0_CORE0_UNCORR_ERRAGG	ESM_LVL_EVENT_48	Level
R5SS0_CORE1_CORR_ERRAGG	ESM_LVL_EVENT_49	Level
R5SS0_CORE1_UNCORR_ERRAGG	ESM_LVL_EVENT_50	Level
R5SS1_CORE0_CORR_ERRAGG	ESM_LVL_EVENT_55	Level
R5SS1_CORE0_UNCORR_ERRAGG	ESM_LVL_EVENT_56	Level
R5SS1_CORE1_CORR_ERRAGG	ESM_LVL_EVENT_57	Level
R5SS1_CORE1_UNCORR_ERRAGG	ESM_LVL_EVENT_58	Level

The correctable aggregator collects EVNTBUS signals [22, 23, 24, 25, 40, 41, 42] and the uncorrectable aggregator collects EVNTBUS signals [33, 34, 37, 38, 39] [2].

2. System SRAM (L2OCRAM, MBOX, TPTC) — via ECC Aggregator 0: This is the path that maps to the soc_eccagg_uncorr_level event you observed. ECC Aggregator 0 protects these specific memories [3]:

L2OCRAM_BANK0 through L2OCRAM_BANK5 (6 banks)
MBOX_SRAM
TPTC_A0, TPTC_A1

The aggregator outputs two Level-type signals to the ESM [4]:

SOC_ECCAGGR_UNCORR_LVL_0 — for double-bit (DED) uncorrectable errors
SOC_ECCAGGR_CORR_LVL_0 — for single-bit (SEC) correctable errors

The six sram*_ecc_uncorr_pulse events you found likely correspond to the six L2OCRAM bank instances (BANK0–BANK5) before they are aggregated into the single SOC_ECCAGGR_UNCORR_LVL_0 signal. The SDK examples use the aggregated Level event because that's the final ESM interface.

Initialization Sequence

The SDK provides a clear initialization pattern. Here's the sequence for MSS L2 RAM as an example [5]:

Step 1: Initialize the target memory

/* Clear Done memory */

SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_DONE_ADDR, 0xfu);

/* Initialize MSS L2 memory (Bank 3 in this example) */

SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);

while(SDL_REG32_RD(SDL_MSS_L2_MEM_INIT_DONE_ADDR) != SDL_ECC_MSS_L2_BANK_MEM_INIT);

/* Clear Done memory after init */

SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_DONE_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);

Step 2: Clear any pre-existing error status

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SaveCopy

SDL_REG32_WR(SDL_ECC_AGGR_ERROR_STATUS1_ADDR, 0xF0Fu);

Step 3: Initialize ECC memory for the aggregator

result = SDL_ECC_initMemory(SDL_SOC_ECC_AGGR, SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID);

Step 4: Configure and initialize ESM with event bitmaps

⌄

SDL_ESM_config ECC_Test_esmInitConfig_MAIN = {

.esmErrorConfig = {1u, 8u},

.enableBitmap = {0x00180000u, 0x00000000u, ...},

.priorityBitmap = {0x00180000u, 0x00000000u, ...},

.errorpinBitmap = {0x00180000u, 0x00000000u, ...},

};

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0,

&ECC_Test_esmInitConfig_MAIN,

SDL_ESM_applicationCallbackFunction, ptr);

The bitmap values (0x00180000u = bits 19 and 20 in group 0) select which ESM events to enable, prioritize, and route to the error pin [5].

Step 5: Initialize the ECC aggregator

static SDL_ECC_MemSubType ECC_Test_MSS_L2_subMemTypeList[] = {

SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID,

};

static SDL_ECC_InitConfig_t ECC_Test_MSS_L2_ECCInitConfig = {

.numRams = 1,

.pMemSubTypeList = &(ECC_Test_MSS_L2_subMemTypeList[0]),

};

result = SDL_ECC_init(SDL_SOC_ECC_AGGR, &ECC_Test_MSS_L2_ECCInitConfig);

Important: ECC aggregators should be configured at startup, after running BIST [6].

Fault Injection

The SDK provides SDL_ECC_injectError() for testing. For wrapper-type RAM IDs (like SRAM), you must access the memory after injection to trigger the ESM event — the hardware detects the error during the read operation [7].

Single-bit (SEC) error injection:

SDL_ECC_InjectErrorConfig_t injectErrorConfig;

injectErrorConfig.pErrMem = (uint32_t *)(0x70100008u); /* MSS_L2 address */

injectErrorConfig.flipBitMask = 0x002; /* Flip 1 bit */

result = SDL_ECC_injectError(SDL_SOC_ECC_AGGR,

SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID,

SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,

&injectErrorConfig);

/* Must access memory to trigger the error event */

testLocationValue = injectErrorConfig.pErrMem[0];

Double-bit (DED) error injection:

injectErrorConfig.pErrMem = (uint32_t *)(0x70100008u);

injectErrorConfig.flipBitMask = 0x03; /* Flip 2 bits */

result = SDL_ECC_injectError(SDL_SOC_ECC_AGGR,

SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID,

SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,

&injectErrorConfig);

testLocationValue = injectErrorConfig.pErrMem[0];

ESM Callback handling:

When the ESM fires, your callback receives the error details. Use SDL_ECC_getESMErrorInfo() and SDL_ECC_getErrorInfo() to identify the exact memory, RAM ID, and bit offset, then clear the pending interrupt [5]:

SDL_ECC_getESMErrorInfo(esmInst, intSrc, &eccmemtype, &eccIntrSrc);

SDL_ECC_getErrorInfo(eccmemtype, eccIntrSrc, &eccErrorInfo);

SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType,

eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT,

eccErrorInfo.injectBitErrCnt);

SDL_ECC_ackIntr(eccmemtype, eccIntrSrc);

For R5F ATCM/BTCM specifically, you also need to enable ECC and the event bus before initialization [5]:

SDL_ECC_UTILS_enableECCATCM();

SDL_UTILS_enable_event_bus();

The MSS_CTRL registers (R5SS*_CPU*_ECC_CORR_ERRAGG_MASK, _STATUS, _STATUS_RAW) control masking and status for the R5F memory error aggregation [2].

To help refine this further, it would be helpful to know:

Whether you need to monitor specific SRAM banks (e.g., only certain L2OCRAM banks) or all RAM types
Whether you need both correctable (SEC) and uncorrectable (DED) error handling, or only uncorrectable
The exact ESM event numbers and bitmap positions for the individual sram*_ecc_uncorr_pulse events — these aren't fully mapped in the available SDK documentation and may require consulting the device-specific ESM event table in the TRM
Whether the six individual SRAM pulse events can be monitored directly at the ESM or only through the aggregated SOC_ECCAGGR Level signals

0 Carwyn Griffiths 9 days ago in reply to Nilabh Anand

Prodigy 90 points

Hi Nilabh,

Thanks for providing the above information and clarifying the purpose of those six SRAM ECC events for the ESM.

Could you clarify, for the initialization sequence above, do steps 1-3 need to be performed in the bootloader before the application is transferred from flash memory to RAM?

Thanks,

Carwyn

0 Nilabh Anand 9 days ago in reply to Carwyn Griffiths

TI__Guru 57110 points

Yes doing it in SBL insures that the check is done before application starts to boot.

Processors

Processors forum

AM263P4-Q1: SRAM ECC checking

Two Error Paths to ESM

Initialization Sequence

Step 1: Initialize the target memory

Step 2: Clear any pre-existing error status

Step 3: Initialize ECC memory for the aggregator

Step 4: Configure and initialize ESM with event bitmaps

Step 5: Initialize the ECC aggregator

Fault Injection

Single-bit (SEC) error injection:

Double-bit (DED) error injection:

ESM Callback handling: