AM6442: Problem initialization of SPI Multi Controller with more than 3 SPI peripherals

Mathias Agren1

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

When I try to assign more than 3 peripherals (Chip selects) on SPI0 using Sysconfig (11_00_00_18) the driver initialization (Drivers_mcspiOpen) fails.
Code is running on R5_0_0 core. The SPI-instance is configured as "Multi Controller" with 4 MCSPI Channel Configurations

The failure occurs in Udma_rmAllocTxCh which appears to hava a limit of 3 DMA-tx-channels for all SPI interfaces combined. It looks like it tries to allocate one channel per CS.

Not sure what DMA-tx-channels means in this context but I don't see why each SPI instance would need more than 1 DMA channel for tx and 1 DMA channel for rx.

Any reason for this failure? Am I configuring the SPI wrong in Sysconfig?

Best Regards,

Mathias

3 months ago

0 Vaibhav Kumar 3 months ago

TI__Guru 57925 points

Hi Mathias,

Mathias Agren1 said:
Any reason for this failure? Am I configuring the SPI wrong in Sysconfig?

I would have you look at the MCSPI Integration Guide: [FAQ] SK-AM64B: MCSPI Integration Guide

Additionally please refer the SDK example: https://github.com/TexasInstruments/mcupsdk-core/tree/next/examples/drivers/mcspi/mcspi_loopback_multi_instances_multi_channels_lld

and https://github.com/TexasInstruments/mcupsdk-core/tree/next/test/drivers/mcspi/mcspi_controller_peripheral_dma

Additionally share your example.syscfg file and tell me if its a r5fs00 noRTOS or freeRTOS example.

Regards,

Vaibhav

0 Mathias Agren1 3 months ago in reply to Vaibhav Kumar

Prodigy 120 points

Problem occurs when running the mcspi_loopback_multi_instances_multi_channels_lld freeRTOS example if I add a 4th CS to CONFIG_MCSPI1 (original example only has 3 CS configured).

I then get the following error:

MAIN_Cortex_R5_0_0: ASSERT: 0.8121s: mcspi/v0/lld/dma/udma/mcspi_dma_udma.c:MCSPI_udmaInitTxCh:342: UDMA_SOK == retVal failed !!!

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM64x" --part "Default" --package "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM64x@11.00.00"
 * @v2CliArgs --device "AM6442" --package "FCBGA (ALV)" --variant "AM6442-D" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM64x@11.00.00"
 * @versions {"tool":"1.22.0+3893"}
 */

/**
 * Import the modules used in this configuration.
 */
const mcspi           = scripting.addModule("/drivers/mcspi/mcspi", {}, false);
const mcspi1          = mcspi.addInstance();
const mcspi2          = mcspi.addInstance();
const mcspi3          = mcspi.addInstance();
const debug_log       = scripting.addModule("/kernel/dpl/debug_log");
const dpl_cfg         = scripting.addModule("/kernel/dpl/dpl_cfg");
const mpu_armv7       = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71      = mpu_armv7.addInstance();
const mpu_armv72      = mpu_armv7.addInstance();
const mpu_armv73      = mpu_armv7.addInstance();
const mpu_armv74      = mpu_armv7.addInstance();
const mpu_armv75      = mpu_armv7.addInstance();
const mpu_armv76      = mpu_armv7.addInstance();
const default_linker  = scripting.addModule("/memory_configurator/default_linker", {}, false);
const default_linker1 = default_linker.addInstance();
const general         = scripting.addModule("/memory_configurator/general", {}, false);
const general1        = general.addInstance();
const region          = scripting.addModule("/memory_configurator/region", {}, false);
const region1         = region.addInstance();
const section         = scripting.addModule("/memory_configurator/section", {}, false);
const section1        = section.addInstance();
const section2        = section.addInstance();
const section3        = section.addInstance();
const section4        = section.addInstance();
const section5        = section.addInstance();
const section6        = section.addInstance();
const section7        = section.addInstance();
const section8        = section.addInstance();
const section9        = section.addInstance();
const section10       = section.addInstance();
const section11       = section.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
mcspi1.$name                       = "CONFIG_MCSPI0";
mcspi1.sdkInfra                    = "LLD";
mcspi1.inputSelect                 = "0";
mcspi1.transferCallbackFxn         = "MCSPI_lld_intrTransferCallback";
mcspi1.errorCallbackFxn            = "MCSPI_lld_intrErrorCallback";
mcspi1.intrEnable                  = "POLLED";
mcspi1.mode                        = "MULTI_CONTROLLER";
mcspi1.SPI.$assign                 = "SPI0";
mcspi1.child.$name                 = "drivers_mcspi_v0_mcspi_v0_template_lld0";
mcspi1.mcspiChannel.create(3);
mcspi1.mcspiChannel[0].$name       = "CONFIG_MCSPI_CH0";
mcspi1.mcspiChannel[0].CSn.$assign = "SPI0_CS0";
mcspi1.mcspiChannel[1].$name       = "CONFIG_MCSPI_CH3";
mcspi1.mcspiChannel[1].CSn.$assign = "SPI0_CS1";
mcspi1.mcspiChannel[2].$name       = "CONFIG_MCSPI_CH4";

mcspi2.$name                       = "CONFIG_MCSPI1";
mcspi2.sdkInfra                    = "LLD";
mcspi2.dpe0                        = "DISABLE";
mcspi2.dpe1                        = "ENABLE";
mcspi2.intrEnable                  = "DMA";
mcspi2.transferMode                = "CALLBACK";
mcspi2.transferCallbackFxn         = "MCSPI_lld_transferCallback";
mcspi2.errorCallbackFxn            = "MCSPI_lld_errorCallback";
mcspi2.mode                        = "MULTI_CONTROLLER";
mcspi2.child.$name                 = "drivers_mcspi_v0_mcspi_v0_template_lld1";
mcspi2.mcspiChannel.create(4);
mcspi2.mcspiChannel[0].$name       = "CONFIG_MCSPI_CH5";
mcspi2.mcspiChannel[0].CSn.$assign = "PRG0_PRU0_GPO17";
mcspi2.mcspiChannel[1].$name       = "CONFIG_MCSPI_CH1";
mcspi2.mcspiChannel[1].CSn.$assign = "PRG0_PRU0_GPO15";
mcspi2.mcspiChannel[2].$name       = "CONFIG_MCSPI_CH2";
mcspi2.mcspiChannel[2].CSn.$assign = "PRG1_PRU1_GPO19";
mcspi2.mcspiChannel[3].$name       = "CONFIG_MCSPI_CH10";
mcspi2.mcspiChannel[3].CSn.$assign = "PRG1_PRU1_GPO7";

mcspi3.$name                 = "CONFIG_MCSPI2";
mcspi3.dpe0                  = "DISABLE";
mcspi3.dpe1                  = "ENABLE";
mcspi3.sdkInfra              = "LLD";
mcspi3.errorCallbackFxn      = "MCSPI_lld_intrErrorCallback";
mcspi3.transferCallbackFxn   = "MCSPI_lld_intrTransferCallback";
mcspi3.mode                  = "MULTI_CONTROLLER";
mcspi3.child.$name           = "drivers_mcspi_v0_mcspi_v0_template_lld2";
mcspi3.mcspiChannel.create(4);
mcspi3.mcspiChannel[0].$name = "CONFIG_MCSPI_CH6";
mcspi3.mcspiChannel[1].$name = "CONFIG_MCSPI_CH7";
mcspi3.mcspiChannel[2].$name = "CONFIG_MCSPI_CH8";
mcspi3.mcspiChannel[3].$name = "CONFIG_MCSPI_CH9";

const udma        = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1       = udma.addInstance({}, false);
udma1.$name       = "CONFIG_UDMA0";
mcspi2.udmaDriver = udma1;

debug_log.enableUartLog            = true;
debug_log.uartLog.$name            = "CONFIG_UART0";
debug_log.uartLog.UART.$assign     = "USART0";
debug_log.uartLog.UART.RXD.$assign = "UART0_RXD";
debug_log.uartLog.UART.TXD.$assign = "UART0_TXD";

const uart_v0_template  = scripting.addModule("/drivers/uart/v0/uart_v0_template", {}, false);
const uart_v0_template1 = uart_v0_template.addInstance({}, false);
uart_v0_template1.$name = "drivers_uart_v0_uart_v0_template0";
debug_log.uartLog.child = uart_v0_template1;

mpu_armv71.$name             = "CONFIG_MPU_REGION0";
mpu_armv71.size              = 31;
mpu_armv71.attributes        = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute      = false;

mpu_armv72.$name             = "CONFIG_MPU_REGION1";
mpu_armv72.size              = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv73.$name             = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr          = 0x41010000;
mpu_armv73.size              = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv74.$name             = "CONFIG_MPU_REGION3";
mpu_armv74.baseAddr          = 0x70000000;
mpu_armv74.size              = 21;
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv75.$name             = "CONFIG_MPU_REGION4";
mpu_armv75.baseAddr          = 0x60000000;
mpu_armv75.size              = 28;
mpu_armv75.accessPermissions = "Supervisor RD, User RD";

mpu_armv76.$name    = "CONFIG_MPU_REGION5";
mpu_armv76.baseAddr = 0x80000000;
mpu_armv76.size     = 31;

default_linker1.$name = "memory_configurator_default_linker0";

general1.$name        = "CONFIG_GENERAL0";
general1.linker.$name = "TIARMCLANG0";

region1.$name                               = "MEMORY_REGION_CONFIGURATION0";
region1.memory_region.create(9);
region1.memory_region[0].type               = "TCMA_R5F";
region1.memory_region[0].$name              = "R5F_VECS";
region1.memory_region[0].size               = 0x40;
region1.memory_region[0].auto               = false;
region1.memory_region[1].type               = "TCMA_R5F";
region1.memory_region[1].$name              = "R5F_TCMA";
region1.memory_region[1].size               = 0x7FC0;
region1.memory_region[2].type               = "TCMB_R5F";
region1.memory_region[2].$name              = "R5F_TCMB0";
region1.memory_region[2].size               = 0x8000;
region1.memory_region[3].$name              = "NON_CACHE_MEM";
region1.memory_region[3].auto               = false;
region1.memory_region[3].manualStartAddress = 0x70060000;
region1.memory_region[3].size               = 0x8000;
region1.memory_region[4].$name              = "MSRAM";
region1.memory_region[4].auto               = false;
region1.memory_region[4].manualStartAddress = 0x70080000;
region1.memory_region[4].size               = 0x40000;
region1.memory_region[5].type               = "FLASH";
region1.memory_region[5].$name              = "FLASH";
region1.memory_region[5].auto               = false;
region1.memory_region[5].manualStartAddress = 0x60100000;
region1.memory_region[5].size               = 0x80000;
region1.memory_region[6].$name              = "USER_SHM_MEM";
region1.memory_region[6].auto               = false;
region1.memory_region[6].manualStartAddress = 0x701D0000;
region1.memory_region[6].size               = 0x80;
region1.memory_region[6].isShared           = true;
region1.memory_region[6].shared_cores       = ["a53ss0-0","a53ss0-1","m4fss0-0","r5fss0-1","r5fss1-0","r5fss1-1"];
region1.memory_region[7].auto               = false;
region1.memory_region[7].manualStartAddress = 0x701D0080;
region1.memory_region[7].size               = 0x3F80;
region1.memory_region[7].$name              = "LOG_SHM_MEM";
region1.memory_region[7].isShared           = true;
region1.memory_region[7].shared_cores       = ["a53ss0-0","a53ss0-1","m4fss0-0","r5fss0-1","r5fss1-0","r5fss1-1"];
region1.memory_region[8].auto               = false;
region1.memory_region[8].manualStartAddress = 0x701D4000;
region1.memory_region[8].size               = 0xC000;
region1.memory_region[8].$name              = "RTOS_NORTOS_IPC_SHM_MEM";
region1.memory_region[8].isShared           = true;
region1.memory_region[8].shared_cores       = ["a53ss0-0","a53ss0-1","m4fss0-0","r5fss0-1","r5fss1-0","r5fss1-1"];

section1.$name                        = "Vector Table";
section1.load_memory                  = "R5F_VECS";
section1.group                        = false;
section1.output_section.create(1);
section1.output_section[0].$name      = ".vectors";
section1.output_section[0].palignment = true;

section2.$name                        = "Text Segments";
section2.load_memory                  = "MSRAM";
section2.output_section.create(5);
section2.output_section[0].$name      = ".text.hwi";
section2.output_section[0].palignment = true;
section2.output_section[1].$name      = ".text.cache";
section2.output_section[1].palignment = true;
section2.output_section[2].$name      = ".text.mpu";
section2.output_section[2].palignment = true;
section2.output_section[3].$name      = ".text.boot";
section2.output_section[3].palignment = true;
section2.output_section[4].$name      = ".text:abort";
section2.output_section[4].palignment = true;

section3.$name                        = "Code and Read-Only Data";
section3.load_memory                  = "MSRAM";
section3.output_section.create(2);
section3.output_section[0].$name      = ".text";
section3.output_section[0].palignment = true;
section3.output_section[1].$name      = ".rodata";
section3.output_section[1].palignment = true;

section4.$name                        = "Data Segment";
section4.load_memory                  = "MSRAM";
section4.output_section.create(1);
section4.output_section[0].$name      = ".data";
section4.output_section[0].palignment = true;

section5.$name                                   = "Memory Segments";
section5.load_memory                             = "MSRAM";
section5.output_section.create(3);
section5.output_section[0].$name                 = ".bss";
section5.output_section[0].palignment            = true;
section5.output_section[0].output_sections_start = "__BSS_START";
section5.output_section[0].output_sections_end   = "__BSS_END";
section5.output_section[1].$name                 = ".sysmem";
section5.output_section[1].palignment            = true;
section5.output_section[2].$name                 = ".stack";
section5.output_section[2].palignment            = true;

section6.$name                                    = "Stack Segments";
section6.load_memory                              = "MSRAM";
section6.output_section.create(5);
section6.output_section[0].$name                  = ".irqstack";
section6.output_section[0].output_sections_start  = "__IRQ_STACK_START";
section6.output_section[0].output_sections_end    = "__IRQ_STACK_END";
section6.output_section[0].input_section.create(1);
section6.output_section[0].input_section[0].$name = ". = . + __IRQ_STACK_SIZE;";
section6.output_section[1].$name                  = ".fiqstack";
section6.output_section[1].output_sections_start  = "__FIQ_STACK_START";
section6.output_section[1].output_sections_end    = "__FIQ_STACK_END";
section6.output_section[1].input_section.create(1);
section6.output_section[1].input_section[0].$name = ". = . + __FIQ_STACK_SIZE;";
section6.output_section[2].$name                  = ".svcstack";
section6.output_section[2].output_sections_start  = "__SVC_STACK_START";
section6.output_section[2].output_sections_end    = "__SVC_STACK_END";
section6.output_section[2].input_section.create(1);
section6.output_section[2].input_section[0].$name = ". = . + __SVC_STACK_SIZE;";
section6.output_section[3].$name                  = ".abortstack";
section6.output_section[3].output_sections_start  = "__ABORT_STACK_START";
section6.output_section[3].output_sections_end    = "__ABORT_STACK_END";
section6.output_section[3].input_section.create(1);
section6.output_section[3].input_section[0].$name = ". = . + __ABORT_STACK_SIZE;";
section6.output_section[4].$name                  = ".undefinedstack";
section6.output_section[4].output_sections_start  = "__UNDEFINED_STACK_START";
section6.output_section[4].output_sections_end    = "__UNDEFINED_STACK_END";
section6.output_section[4].input_section.create(1);
section6.output_section[4].input_section[0].$name = ". = . + __UNDEFINED_STACK_SIZE;";

section7.$name                        = "Initialization and Exception Handling";
section7.load_memory                  = "MSRAM";
section7.output_section.create(3);
section7.output_section[0].$name      = ".ARM.exidx";
section7.output_section[0].palignment = true;
section7.output_section[1].$name      = ".init_array";
section7.output_section[1].palignment = true;
section7.output_section[2].$name      = ".fini_array";
section7.output_section[2].palignment = true;

section8.$name                       = "User Shared Memory";
section8.type                        = "NOLOAD";
section8.load_memory                 = "USER_SHM_MEM";
section8.group                       = false;
section8.output_section.create(1);
section8.output_section[0].$name     = ".bss.user_shared_mem";
section8.output_section[0].alignment = 0;

section9.$name                       = "Log Shared Memory";
section9.load_memory                 = "LOG_SHM_MEM";
section9.type                        = "NOLOAD";
section9.group                       = false;
section9.output_section.create(1);
section9.output_section[0].$name     = ".bss.log_shared_mem";
section9.output_section[0].alignment = 0;

section10.$name                       = "IPC Shared Memory";
section10.type                        = "NOLOAD";
section10.load_memory                 = "RTOS_NORTOS_IPC_SHM_MEM";
section10.group                       = false;
section10.output_section.create(1);
section10.output_section[0].$name     = ".bss.ipc_vring_mem";
section10.output_section[0].alignment = 0;

section11.$name                       = "Non Cacheable Memory";
section11.load_memory                 = "NON_CACHE_MEM";
section11.group                       = false;
section11.type                        = "NOLOAD";
section11.output_section.create(1);
section11.output_section[0].$name     = ".bss.nocache";
section11.output_section[0].alignment = 0;

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
mcspi1.SPI.CLK.$suggestSolution             = "SPI0_CLK";
mcspi1.SPI.D0.$suggestSolution              = "SPI0_D0";
mcspi1.SPI.D1.$suggestSolution              = "SPI0_D1";
mcspi1.mcspiChannel[2].CSn.$suggestSolution = "UART0_CTSn";
mcspi2.SPI.$suggestSolution                 = "SPI3";
mcspi2.SPI.CLK.$suggestSolution             = "PRG0_PRU0_GPO16";
mcspi2.SPI.D0.$suggestSolution              = "PRG0_PRU0_GPO13";
mcspi2.SPI.D1.$suggestSolution              = "PRG0_PRU0_GPO14";
mcspi3.SPI.$suggestSolution                 = "SPI1";
mcspi3.SPI.CLK.$suggestSolution             = "SPI1_CLK";
mcspi3.SPI.D0.$suggestSolution              = "SPI1_D0";
mcspi3.SPI.D1.$suggestSolution              = "SPI1_D1";
mcspi3.mcspiChannel[0].CSn.$suggestSolution = "UART1_RTSn";
mcspi3.mcspiChannel[1].CSn.$suggestSolution = "UART1_CTSn";
mcspi3.mcspiChannel[2].CSn.$suggestSolution = "SPI1_CS1";
mcspi3.mcspiChannel[3].CSn.$suggestSolution = "SPI1_CS0";

0 Vaibhav Kumar 3 months ago in reply to Mathias Agren1

TI__Guru 57925 points

Hi Mathias,

Please share the generated file "ti_drivers_open_close.c" in your application.

Regards,

Vaibhav

0 Mathias Agren1 3 months ago in reply to Vaibhav Kumar

Prodigy 120 points

Hi Vaibhav,

/*
 *  Copyright (C) 2021 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Auto generated file
 */

#include "ti_drivers_open_close.h"
#include <kernel/dpl/DebugP.h>

void Drivers_open(void)
{
    Drivers_udmaOpen();
    Drivers_mcspiOpen();
    Drivers_uartOpen();
}

void Drivers_close(void)
{
    Drivers_udmaClose();
    Drivers_mcspiClose();
    Drivers_uartClose();
}

/*
 * UDMA
 */

void Drivers_udmaOpen(void)
{
}

void Drivers_udmaClose(void)
{
}

/*
 * MCSPI
 */
#include <drivers/mcspi/v0/lld/mcspi_lld.h>

/* MCSPI Driver handles */
MCSPILLD_Object gMcspiObject[CONFIG_MCSPI_NUM_INSTANCES];
MCSPILLD_Handle gMcspiHandle[CONFIG_MCSPI_NUM_INSTANCES];

extern MCSPILLD_InitObject gMcspiInitObject[];

extern MCSPI_ChConfig gConfigMcspi0ChCfg[];
extern MCSPI_ChConfig gConfigMcspi1ChCfg[];
extern MCSPI_ChConfig gConfigMcspi2ChCfg[];


#include <drivers/mcspi/v0/lld/dma/udma/mcspi_dma_udma.h>
#include <drivers/udma.h>

/*
 * Ring parameters
 */
/** \brief Number of ring entries - we can prime this much ADC operations */
#define MCSPI_UDMA_TEST_RING_ENTRIES          (1U)
/** \brief Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
#define MCSPI_UDMA_TEST_RING_ENTRY_SIZE       (sizeof(uint64_t))
/** \brief Total ring memory */
#define MCSPI_UDMA_TEST_RING_MEM_SIZE         (MCSPI_UDMA_TEST_RING_ENTRIES * MCSPI_UDMA_TEST_RING_ENTRY_SIZE)
/** \brief UDMA host mode buffer descriptor memory size. */
#define MCSPI_UDMA_TEST_DESC_SIZE             (sizeof(CSL_UdmapCppi5HMPD))


/* MCSPI Driver DMA Channel Configurations */
/* MCSPI UDMA TX Channel Objects */
static Udma_ChObject gMcspi1UdmaTxChObj0;

/* MCSPI UDMA RX Channel Objects */
static Udma_ChObject gMcspi1UdmaRxChObj0;

/**< UDMA TX completion queue object */
static Udma_EventObject        gMcspi1UdmaCqTxEventObjCh0;
/**< UDMA RX completion queue object */
static Udma_EventObject        gMcspi1UdmaCqRxEventObjCh0;

/* MCSPI UDMA Channel Ring Mem */
static uint8_t gMcspi1UdmaRxRingMemCh0[MCSPI_UDMA_TEST_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gMcspi1UdmaTxRingMemCh0[MCSPI_UDMA_TEST_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));

/* MCSPI UDMA Channel HPD Mem */
static uint8_t gMcspi1UdmaTxHpdMemCh0[MCSPI_UDMA_TEST_DESC_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gMcspi1UdmaRxHpdMemCh0[MCSPI_UDMA_TEST_DESC_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
/* MCSPI UDMA TX Channel Objects */
static Udma_ChObject gMcspi1UdmaTxChObj1;

/* MCSPI UDMA RX Channel Objects */
static Udma_ChObject gMcspi1UdmaRxChObj1;

/**< UDMA TX completion queue object */
static Udma_EventObject        gMcspi1UdmaCqTxEventObjCh1;
/**< UDMA RX completion queue object */
static Udma_EventObject        gMcspi1UdmaCqRxEventObjCh1;

/* MCSPI UDMA Channel Ring Mem */
static uint8_t gMcspi1UdmaRxRingMemCh1[MCSPI_UDMA_TEST_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gMcspi1UdmaTxRingMemCh1[MCSPI_UDMA_TEST_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));

/* MCSPI UDMA Channel HPD Mem */
static uint8_t gMcspi1UdmaTxHpdMemCh1[MCSPI_UDMA_TEST_DESC_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gMcspi1UdmaRxHpdMemCh1[MCSPI_UDMA_TEST_DESC_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
/* MCSPI UDMA TX Channel Objects */
static Udma_ChObject gMcspi1UdmaTxChObj2;

/* MCSPI UDMA RX Channel Objects */
static Udma_ChObject gMcspi1UdmaRxChObj2;

/**< UDMA TX completion queue object */
static Udma_EventObject        gMcspi1UdmaCqTxEventObjCh2;
/**< UDMA RX completion queue object */
static Udma_EventObject        gMcspi1UdmaCqRxEventObjCh2;

/* MCSPI UDMA Channel Ring Mem */
static uint8_t gMcspi1UdmaRxRingMemCh2[MCSPI_UDMA_TEST_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gMcspi1UdmaTxRingMemCh2[MCSPI_UDMA_TEST_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));

/* MCSPI UDMA Channel HPD Mem */
static uint8_t gMcspi1UdmaTxHpdMemCh2[MCSPI_UDMA_TEST_DESC_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gMcspi1UdmaRxHpdMemCh2[MCSPI_UDMA_TEST_DESC_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
/* MCSPI UDMA TX Channel Objects */
static Udma_ChObject gMcspi1UdmaTxChObj3;

/* MCSPI UDMA RX Channel Objects */
static Udma_ChObject gMcspi1UdmaRxChObj3;

/**< UDMA TX completion queue object */
static Udma_EventObject        gMcspi1UdmaCqTxEventObjCh3;
/**< UDMA RX completion queue object */
static Udma_EventObject        gMcspi1UdmaCqRxEventObjCh3;

/* MCSPI UDMA Channel Ring Mem */
static uint8_t gMcspi1UdmaRxRingMemCh3[MCSPI_UDMA_TEST_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gMcspi1UdmaTxRingMemCh3[MCSPI_UDMA_TEST_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));

/* MCSPI UDMA Channel HPD Mem */
static uint8_t gMcspi1UdmaTxHpdMemCh3[MCSPI_UDMA_TEST_DESC_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gMcspi1UdmaRxHpdMemCh3[MCSPI_UDMA_TEST_DESC_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));

MCSPI_UdmaChConfig gConfigMcspi1DmaChCfg[CONFIG_MCSPI1_NUM_CH] =
{
    {
        .txChHandle       = &gMcspi1UdmaTxChObj0,
        .rxChHandle       = &gMcspi1UdmaRxChObj0,
        .cqTxEvtHandle    = &gMcspi1UdmaCqTxEventObjCh0,
        .cqRxEvtHandle    = &gMcspi1UdmaCqRxEventObjCh0,
        .txHpdMem         = &gMcspi1UdmaTxHpdMemCh0,
        .rxHpdMem         = &gMcspi1UdmaRxHpdMemCh0,
        .hpdMemSize       = MCSPI_UDMA_TEST_DESC_SIZE,
        .txRingMem        = &gMcspi1UdmaTxRingMemCh0,
        .rxRingMem        = &gMcspi1UdmaRxRingMemCh0,
        .ringMemSize      = MCSPI_UDMA_TEST_RING_MEM_SIZE,
        .ringElemCnt      = MCSPI_UDMA_TEST_RING_ENTRIES,
        .rxEvtNum         = UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX,
        .txEvtNum         = UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX,
        .isOpen           = FALSE,
    },
    {
        .txChHandle       = &gMcspi1UdmaTxChObj1,
        .rxChHandle       = &gMcspi1UdmaRxChObj1,
        .cqTxEvtHandle    = &gMcspi1UdmaCqTxEventObjCh1,
        .cqRxEvtHandle    = &gMcspi1UdmaCqRxEventObjCh1,
        .txHpdMem         = &gMcspi1UdmaTxHpdMemCh1,
        .rxHpdMem         = &gMcspi1UdmaRxHpdMemCh1,
        .hpdMemSize       = MCSPI_UDMA_TEST_DESC_SIZE,
        .txRingMem        = &gMcspi1UdmaTxRingMemCh1,
        .rxRingMem        = &gMcspi1UdmaRxRingMemCh1,
        .ringMemSize      = MCSPI_UDMA_TEST_RING_MEM_SIZE,
        .ringElemCnt      = MCSPI_UDMA_TEST_RING_ENTRIES,
        .rxEvtNum         = UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX,
        .txEvtNum         = UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX,
        .isOpen           = FALSE,
    },
    {
        .txChHandle       = &gMcspi1UdmaTxChObj2,
        .rxChHandle       = &gMcspi1UdmaRxChObj2,
        .cqTxEvtHandle    = &gMcspi1UdmaCqTxEventObjCh2,
        .cqRxEvtHandle    = &gMcspi1UdmaCqRxEventObjCh2,
        .txHpdMem         = &gMcspi1UdmaTxHpdMemCh2,
        .rxHpdMem         = &gMcspi1UdmaRxHpdMemCh2,
        .hpdMemSize       = MCSPI_UDMA_TEST_DESC_SIZE,
        .txRingMem        = &gMcspi1UdmaTxRingMemCh2,
        .rxRingMem        = &gMcspi1UdmaRxRingMemCh2,
        .ringMemSize      = MCSPI_UDMA_TEST_RING_MEM_SIZE,
        .ringElemCnt      = MCSPI_UDMA_TEST_RING_ENTRIES,
        .rxEvtNum         = UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX,
        .txEvtNum         = UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX,
        .isOpen           = FALSE,
    },
    {
        .txChHandle       = &gMcspi1UdmaTxChObj3,
        .rxChHandle       = &gMcspi1UdmaRxChObj3,
        .cqTxEvtHandle    = &gMcspi1UdmaCqTxEventObjCh3,
        .cqRxEvtHandle    = &gMcspi1UdmaCqRxEventObjCh3,
        .txHpdMem         = &gMcspi1UdmaTxHpdMemCh3,
        .rxHpdMem         = &gMcspi1UdmaRxHpdMemCh3,
        .hpdMemSize       = MCSPI_UDMA_TEST_DESC_SIZE,
        .txRingMem        = &gMcspi1UdmaTxRingMemCh3,
        .rxRingMem        = &gMcspi1UdmaRxRingMemCh3,
        .ringMemSize      = MCSPI_UDMA_TEST_RING_MEM_SIZE,
        .ringElemCnt      = MCSPI_UDMA_TEST_RING_ENTRIES,
        .rxEvtNum         = UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX,
        .txEvtNum         = UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX,
        .isOpen           = FALSE,
    },
};

void Drivers_mcspiOpen(void)
{
    int32_t status = MCSPI_STATUS_SUCCESS;

    gMcspiHandle[CONFIG_MCSPI0]             = &gMcspiObject[CONFIG_MCSPI0];
    gMcspiHandle[CONFIG_MCSPI0]->state      = MCSPI_STATE_RESET;
    gMcspiHandle[CONFIG_MCSPI0]->baseAddr   = CSL_MCSPI0_CFG_BASE;
    gMcspiHandle[CONFIG_MCSPI0]->hMcspiInit = &gMcspiInitObject[CONFIG_MCSPI0];

    status = MCSPI_lld_init(gMcspiHandle[CONFIG_MCSPI0]);
    DebugP_assert(status == MCSPI_STATUS_SUCCESS);

    gMcspiHandle[CONFIG_MCSPI1]             = &gMcspiObject[CONFIG_MCSPI1];
    gMcspiHandle[CONFIG_MCSPI1]->state      = MCSPI_STATE_RESET;
    gMcspiHandle[CONFIG_MCSPI1]->baseAddr   = CSL_MCSPI3_CFG_BASE;
    gMcspiHandle[CONFIG_MCSPI1]->hMcspiInit = &gMcspiInitObject[CONFIG_MCSPI1];

    status = MCSPI_lld_initDma(gMcspiHandle[CONFIG_MCSPI1]);
    DebugP_assert(status == MCSPI_STATUS_SUCCESS);

    gMcspiHandle[CONFIG_MCSPI2]             = &gMcspiObject[CONFIG_MCSPI2];
    gMcspiHandle[CONFIG_MCSPI2]->state      = MCSPI_STATE_RESET;
    gMcspiHandle[CONFIG_MCSPI2]->baseAddr   = CSL_MCSPI1_CFG_BASE;
    gMcspiHandle[CONFIG_MCSPI2]->hMcspiInit = &gMcspiInitObject[CONFIG_MCSPI2];

    status = MCSPI_lld_init(gMcspiHandle[CONFIG_MCSPI2]);
    DebugP_assert(status == MCSPI_STATUS_SUCCESS);

    return;
}

void Drivers_mcspiClose(void)
{
    int32_t status = MCSPI_STATUS_SUCCESS;

    status = MCSPI_lld_deInit(gMcspiHandle[CONFIG_MCSPI0]);
    DebugP_assert(status == MCSPI_STATUS_SUCCESS);

    status = MCSPI_lld_deInitDma(gMcspiHandle[CONFIG_MCSPI1]);
    DebugP_assert(status == MCSPI_STATUS_SUCCESS);

    status = MCSPI_lld_deInit(gMcspiHandle[CONFIG_MCSPI2]);
    DebugP_assert(status == MCSPI_STATUS_SUCCESS);


    return;
}


/*
 * UART
 */

/* UART Driver handles */
UART_Handle gUartHandle[CONFIG_UART_NUM_INSTANCES];

#include <drivers/uart/v0/lld/dma/uart_dma.h>
#include <kernel/dpl/ClockP.h>

UART_DmaChConfig gUartDmaChConfig[CONFIG_UART_NUM_INSTANCES] =
{
                NULL,
};

/* UART Driver Parameters */
UART_Params gUartParams[CONFIG_UART_NUM_INSTANCES] =
{
        {
            .baudRate           = 115200,
            .dataLength         = UART_LEN_8,
            .stopBits           = UART_STOPBITS_1,
            .parityType         = UART_PARITY_NONE,
            .readMode           = UART_TRANSFER_MODE_BLOCKING,
            .readReturnMode     = UART_READ_RETURN_MODE_FULL,
            .writeMode          = UART_TRANSFER_MODE_BLOCKING,
            .readCallbackFxn    = NULL,
            .writeCallbackFxn   = NULL,
            .hwFlowControl      = FALSE,
            .hwFlowControlThr   = UART_RXTRIGLVL_16,
            .transferMode       = UART_CONFIG_MODE_INTERRUPT,
            .skipIntrReg         = FALSE,
            .uartDmaIndex = -1,
            .intrNum            = 210U,
            .intrPriority       = 4U,
            .operMode           = UART_OPER_MODE_16X,
            .rxTrigLvl          = UART_RXTRIGLVL_8,
            .txTrigLvl          = UART_TXTRIGLVL_32,
            .rxEvtNum           = 0U,
            .txEvtNum           = 0U,
        },
};

void Drivers_uartOpen(void)
{
    uint32_t instCnt;
    int32_t  status = SystemP_SUCCESS;

    for(instCnt = 0U; instCnt < CONFIG_UART_NUM_INSTANCES; instCnt++)
    {
        gUartHandle[instCnt] = NULL;   /* Init to NULL so that we can exit gracefully */
    }

    /* Open all instances */
    for(instCnt = 0U; instCnt < CONFIG_UART_NUM_INSTANCES; instCnt++)
    {
        gUartHandle[instCnt] = UART_open(instCnt, &gUartParams[instCnt]);
        if(NULL == gUartHandle[instCnt])
        {
            DebugP_logError("UART open failed for instance %d !!!\r\n", instCnt);
            status = SystemP_FAILURE;
            break;
        }
    }

    if(SystemP_FAILURE == status)
    {
        Drivers_uartClose();   /* Exit gracefully */
    }

    return;
}

void Drivers_uartClose(void)
{
    uint32_t instCnt;

    /* Close all instances that are open */
    for(instCnt = 0U; instCnt < CONFIG_UART_NUM_INSTANCES; instCnt++)
    {
        if(gUartHandle[instCnt] != NULL)
        {
            UART_close(gUartHandle[instCnt]);
            gUartHandle[instCnt] = NULL;
        }
    }

    return;
}

Best Regards,

Mathias

0 Vaibhav Kumar 3 months ago in reply to Mathias Agren1

TI__Guru 57925 points

Hi,

Upon adding 1 more CS, I run into this problem as well:

[MAIN_Cortex_R5_0_0] ASSERT: 0.14053s: mcspi/v0/lld/dma/udma/mcspi_dma_udma.c:MCSPI_udmaInitTxCh:342: UDMA_SOK == retVal failed !!!

I have created a bug to follow up on this and will get this fixed in the coming release.

Regards,

Vaibhav

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AM6442: Problem initialization of SPI Multi Controller with more than 3 SPI peripherals