My customer is looking for verification of the correlation between the SDRCR terminology and the IBIS model terminology. For general relationship between DDR3 controller settings and the IBIS model values and usage. I understand that there are many more cases in IBIS models than can be set in the register. I am just looking at trends that the simulations show and how to correctly set the register to optimize for those trends.
DDR_TERM RZQ = 240 Ohm by external resistor. Is this used to command the DRAM IC ODT mode only on DQ and DQSTROBE when in Write mode when TI is driving?
1h = RZQ/4 -> DRAM IBIS ODT set for 60 Ohms ?
2h = RZQ/2 -> DRAM IBIS ODT set for 120 Ohms ?
3h = RZQ/6 -> DRAM IBIS ODT set for 40 Ohms ?
4h = RZQ/12 -> DRAM IBIS ODT set for 20 Ohms ?
5h = RZQ/8 -> DRAM IBIS ODT set for 30 Ohms ?
DYN_ODT RZQ =240 Ohm by external resistor. Is this used only on the DQ and DQSTROBE in read mode when TI pins are input?
0 = off -> IBIS NO TERM ?
1h = RZQ/4 -> IBIS FULL TERM ?
1h = RZQ/2 -> IBIS HALF TERM ?
SDRAM_DRIVE Does this apply to all DDR3 data (in write mode), strobe (in write mode), address, command, control signal groups unilaterally ?
0 = full -> IBIS fastest ?
1h = ½ -> IBIS fast ?
2h = ¼ -> IBIS slow ?
3h = 1/8 -> IBIS slowest ?
