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DRA821U: Support Required for 10G Interface Configuration on DRA821U

Subashini N

Prodigy 40 points

Part Number: DRA821U
Other Parts Discussed in Thread: SYSCONFIG, DRA821

Hi Team,

We are currently working on validating the 10G interface on the DRA821U processor. We had previously raised a support query (link below) and followed the same configuration in our setup. However, the Ethernet interface is not functioning as expected—link up and link down messages are being printed continuously.

Additionally, there have been updates to the TX and RX pin connections on our board. When we attempt to configure these TX/RX pins using the SysConfig tool, no corresponding entries are generated in the DTSI output. Now, we have only included the MDIO, MDC, and reset pins in the DTSI.

Could you please guide us with the following?

Proper configuration of the 10G TX/RX pins in the DTSI
Guidance to correctly bring up and validate the 10G interface

For reference, our previous query is included below:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1608293/dra821u-guidance-required-for-implementing-10g-interface-on-dra821u/6203863

Pinmux
-------------

Functionality	Pad name	Pin	Power group	GPIO no	INPUT/OUTPUT	IO LEVEL
SGMII1_TX0_N	MCU_RGMII1_TD1/MCU_RMII1_TXD1/WKUP_GPIO0_46	B11	VDDSHV2_MCU	-	Output	1.8V, LVDS
SGMII1_TX0_P	MCU_RGMII1_TD0/MCU_RMII1_TXD0/WKUP_GPIO0_47	D10	VDDSHV2_MCU	-	Output	1.8V, LVDS
SGMII1_RX0_N	MCU_RGMII1_RD1/MCU_RMII1_RXD1/WKUP_GPIO0_52	B9	VDDSHV2_MCU	-	Input	1.8V, LVDS
SGMII1_RX0_P	MCU_RGMII1_RD0/MCU_RMII1_RXD0/WKUP_GPIO0_53	A9	VDDSHV2_MCU	-	Input	1.8V, LVDS
ETH_10G_MDC	MCU_MDIO0_MDC/WKUP_GPIO0_55	D9	VDDSHV2_MCU	-	Output	1.8V, LVCMOS
ETH_10G_MDIO	MCU_MDIO0_MDIO/WKUP_GPIO0_54	C9	VDDSHV2_MCU	-	Input/Output	1.8V, LVCMOS
ETH_10G_RSTn(GPIO_A_1)	EXT_REFCLK1/SYNC1_OUT/CPTS0_HW2TSPUSH/UART3_TXD/SPI7_CLK/I2C1_SDA/GPIO0_59	T3	VDDSHV0	GPIO0_59	Output	1.8V, LVCMOS
ETH_10G_INTn(GPIO_A_0)	ECAP0_IN_APWM_OUT/SYNC0_OUT/CPTS0_RFT_CLK/CPTS0_HW1TSPUSH/UART3_RXD/SPI7_CS0/I2C1_SCL/GPIO0_58	U3	VDDSHV0	GPIO0_58	Input	1.8V, LVCMOS
RSTOUT(GPIO_A_2)	I2C0_SCL/GPIO0_56	V3	VDDSHV0	GPIO0_56	Output	1.8V, LVCMOS
SGMII1_TX0_N	MCU_RGMII1_TD1/MCU_RMII1_TXD1/WKUP_GPIO0_46	B11	VDDSHV2_MCU	-	Output	1.8V, LVDS
SGMII1_TX0_P	MCU_RGMII1_TD0/MCU_RMII1_TXD0/WKUP_GPIO0_47	D10	VDDSHV2_MCU	-	Output	1.8V, LVDS
SGMII1_RX0_N	MCU_RGMII1_RD1/MCU_RMII1_RXD1/WKUP_GPIO0_52	B9	VDDSHV2_MCU	-	Input	1.8V, LVDS
SGMII1_RX0_P	MCU_RGMII1_RD0/MCU_RMII1_RXD0/WKUP_GPIO0_53	A9	VDDSHV2_MCU	-	Input	1.8V, LVDS

Thanks and Regards,

Subashini

0 Doredla Sudheer Kumar 3 months ago

TI__Guru* 79310 points

Hi,

Subashini N said:
Additionally, there have been updates to the TX and RX pin connections on our board. When we attempt to configure these TX/RX pins using the SysConfig tool, no corresponding entries are generated in the DTSI output. Now, we have only included the MDIO, MDC, and reset pins in the DTSI.

SerDes pins are unique and not multiplexed with any other pins these are like SERDES0_TXy_P/N and SERDES0_RXy_P/N.

The selection of SerDes lane is depends upon the serdes_ln_ctrl node in device tree.

Also, note that 10G is supported only from MAC Port-1 on Silicon Revision 2 SoC.

SGMII1 lines are from SERDES0_RX2 and SERDES0_TX2 pins.

Subashini N said:
Additionally, there have been updates to the TX and RX pin connections on our board. When we attempt to configure these TX/RX pins using the SysConfig tool, no corresponding entries are generated in the DTSI output. Now, we have only included the MDIO, MDC, and reset pins in the DTSI.

As mentioned above SerDes pins are not multiplexed with any other pins so, no pin-mux configuration is required.

Subashini N said:
Could you please guide us with the following?

Proper configuration of the 10G TX/RX pins in the DTSI

Guidance to correctly bring up and validate the 10G interface

As mentioned above you need to have SerDes configuration.

Please refer to below E2E, where we supported to enable USXGMII 10G link.
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1609652/dra821u-inquiry-about-10g-native-ethernet-usxgmii-xfi-configuration-on-dra821-sdk-11-1/6207281?tisearch=e2e-sitesearch&keymatch=USXGMII%20on%20DRA821#

Best Regards,
Sudheer

0 Subashini N 3 months ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

As per the reference link you shared, we have updated the DTSI entries and the driver file. However, after these changes, the Ethernet nodes are no longer being detected.

In our setup, both Eth0 (1 Gbps) and Eth1 (10 Gbps) share the same MDC and MDIO pins. After applying the DTSI changes, even Eth0 has stopped working and is not being detected.

We need to validate the 10G PHY through board-to-board testing. Could you please guide us on how to resolve this issue?

For your reference, we have attached the updated DTSI files and test logs.

Details:

SDK Version: 09.02.00.04
Yocto: Kirkstone
SoC: DRA821
Interface Mode: USXGMII / XFI (10G fixed link)

10G part number: 88X3310-A1-BUS4I000

0777.files.zip 3482.testlog.txt

Thanks and Regards,
Subashini

0 Doredla Sudheer Kumar 3 months ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Subashini N said:
In our setup, both Eth0 (1 Gbps) and Eth1 (10 Gbps) share the same MDC and MDIO pins. After applying the DTSI changes, even Eth0 has stopped working and is not being detected.

I believe both are CPSW5G Ports, as MCU CPSW2G is disabled in your configuraiton.

&mcu_cpsw{
status = "disabled";
};

Also, can you please confirm, is ETHFW running from MCU2_0 core? it should not be when CPSW5G is accessed by Linux.

I can see some error from SerDes driver, failed to power on.
[ 2.690810] cdns-torrent-phy 5060000.serdes: Timeout waiting for CMN ready
[ 2.699469] phy phy-5060000.serdes.6: phy poweron failed --> -110
[ 2.708019] am65-cpsw-nuss: probe of c000000.ethernet failed with error -110

It seems like PLL is not locked.

Can you please share SerDes clock dump using k3conf tool.

Also, please share the SerDes register dump.

Best Regards,
Sudheer

0 Subashini N 3 months ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

Can you please share how I can confirm and disable ETHFW? Also, can you share which registers need to be read for the SerDes? Here I have attached the k3conf dump of SerDes clocks.

Fullscreen 6622.clock_dump.txt Download

root@j7200-iwg52m:~# 
root@j7200-iwg52m:~# k3conf dump clocks | grep -i serdes
|    19     |     3    | DEV_CPSW0_SERDES4_RXCLK                                                           | CLK_STATE_READY     | 0               |
|    19     |    14    | DEV_CPSW0_SERDES4_RXFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    32    | DEV_CPSW0_SERDES1_TXCLK                                                           | CLK_STATE_READY     | 0               |
|    19     |    34    | DEV_CPSW0_SERDES2_RXCLK                                                           | CLK_STATE_READY     | 0               |
|    19     |    35    | DEV_CPSW0_SERDES1_RXFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    37    | DEV_CPSW0_SERDES1_TXMCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    38    | DEV_CPSW0_SERDES1_REFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    42    | DEV_CPSW0_SERDES3_TXFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    43    | DEV_CPSW0_SERDES3_RXFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    46    | DEV_CPSW0_SERDES2_TXCLK                                                           | CLK_STATE_READY     | 0               |
|    19     |    47    | DEV_CPSW0_SERDES1_RXCLK                                                           | CLK_STATE_READY     | 0               |
|    19     |    48    | DEV_CPSW0_SERDES1_TXFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    50    | DEV_CPSW0_SERDES2_TXFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    54    | DEV_CPSW0_SERDES4_TXMCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    55    | DEV_CPSW0_SERDES3_TXCLK                                                           | CLK_STATE_READY     | 0               |
|    19     |    56    | DEV_CPSW0_SERDES2_TXMCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    58    | DEV_CPSW0_SERDES4_REFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    59    | DEV_CPSW0_SERDES3_TXMCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    60    | DEV_CPSW0_SERDES2_REFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    61    | DEV_CPSW0_SERDES3_REFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    62    | DEV_CPSW0_SERDES3_RXCLK                                                           | CLK_STATE_READY     | 0               |
|    19     |    64    | DEV_CPSW0_SERDES2_RXFCLK                                                          | CLK_STATE_READY     | 0               |
|    19     |    66    | DEV_CPSW0_SERDES4_TXCLK                                                           | CLK_STATE_READY     | 0               |
|    19     |    67    | DEV_CPSW0_SERDES4_TXFCLK                                                          | CLK_STATE_READY     | 0               |
|   292     |     1    | DEV_SERDES_10G1_IP3_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |     3    | DEV_SERDES_10G1_IP2_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |     4    | DEV_SERDES_10G1_IP1_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |     6    | DEV_SERDES_10G1_IP3_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |     9    | DEV_SERDES_10G1_IP2_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    10    | DEV_SERDES_10G1_IP1_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    11    | DEV_SERDES_10G1_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   292     |    13    | DEV_SERDES_10G1_IP1_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    14    | DEV_SERDES_10G1_IP1_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    15    | DEV_SERDES_10G1_IP2_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    16    | DEV_SERDES_10G1_IP2_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    19    | DEV_SERDES_10G1_IP3_LN1_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    21    | DEV_SERDES_10G1_IP2_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    22    | DEV_SERDES_10G1_IP1_LN2_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    24    | DEV_SERDES_10G1_IP2_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    25    | DEV_SERDES_10G1_IP2_LN1_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    29    | DEV_SERDES_10G1_IP1_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    32    | DEV_SERDES_10G1_IP2_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    33    | DEV_SERDES_10G1_IP2_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    34    | DEV_SERDES_10G1_IP1_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    38    | DEV_SERDES_10G1_IP1_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    40    | DEV_SERDES_10G1_IP2_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    41    | DEV_SERDES_10G1_IP2_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    42    | DEV_SERDES_10G1_IP2_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    43    | DEV_SERDES_10G1_IP2_LN2_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    44    | DEV_SERDES_10G1_IP2_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    45    | DEV_SERDES_10G1_IP1_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    49    | DEV_SERDES_10G1_IP1_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    52    | DEV_SERDES_10G1_IP1_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    55    | DEV_SERDES_10G1_IP1_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    56    | DEV_SERDES_10G1_IP3_LN3_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    59    | DEV_SERDES_10G1_IP2_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    61    | DEV_SERDES_10G1_IP2_LN0_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    62    | DEV_SERDES_10G1_IP2_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    63    | DEV_SERDES_10G1_IP1_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    65    | DEV_SERDES_10G1_IP1_LN3_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    66    | DEV_SERDES_10G1_IP3_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    67    | DEV_SERDES_10G1_IP2_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    73    | DEV_SERDES_10G1_IP3_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    74    | DEV_SERDES_10G1_IP3_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    75    | DEV_SERDES_10G1_IP1_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    77    | DEV_SERDES_10G1_IP1_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    80    | DEV_SERDES_10G1_IP1_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    81    | DEV_SERDES_10G1_IP2_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    82    | DEV_SERDES_10G1_IP2_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    85    | DEV_SERDES_10G1_CORE_REF_CLK                                                      | CLK_STATE_READY     | 156250000       |
|   292     |    86    | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                       | CLK_STATE_READY     | 19200000        |
|   292     |    87    | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                        | CLK_STATE_READY     | 0               |
|   292     |    88    | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK             | CLK_STATE_READY     | 156250000       |
|   292     |    89    | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK             | CLK_STATE_READY     | 100000000       |
|   292     |    92    | DEV_SERDES_10G1_IP1_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    95    | DEV_SERDES_10G1_IP2_LN3_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |    96    | DEV_SERDES_10G1_IP3_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |    98    | DEV_SERDES_10G1_IP3_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |   100    | DEV_SERDES_10G1_IP2_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |   102    | DEV_SERDES_10G1_IP3_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |   104    | DEV_SERDES_10G1_IP1_LN1_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |   107    | DEV_SERDES_10G1_IP3_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |   108    | DEV_SERDES_10G1_IP1_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |   109    | DEV_SERDES_10G1_IP2_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |   111    | DEV_SERDES_10G1_IP1_LN0_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   292     |   112    | DEV_SERDES_10G1_IP2_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |   113    | DEV_SERDES_10G1_IP1_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |   118    | DEV_SERDES_10G1_IP1_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |   124    | DEV_SERDES_10G1_IP1_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   292     |   126    | DEV_SERDES_10G1_IP3_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
root@j7200-iwg52m:~# 
root@j7200-iwg52m:~#

Thanks and Regards,
Subashini

0 Doredla Sudheer Kumar 3 months ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Subashini N said:
Can you please share how I can confirm and disable ETHFW?

You can check firmware loaded to MCU2_0 core, is it ETHFW application or any other application.

You can also perform trace buffer dump using beow command, if trace are enabled in R5F application. By default ETHFW has enabled tracer buffer log.

# cat /sys/kernel/debug/remoteproc/remoteproc*/trace0

Subashini N said:
Also, can you share which registers need to be read for the SerDes? Here I have attached the k3conf dump of SerDes clocks.

You can dump the registers mentiond in folowing debug guide.
https://www.ti.com/lit/ab/sprads2/sprads2.pdf

Best Regards,
Sudheer

0 Subashini N 2 months ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

HI Sudheer,

Apologizes for delayed response. I have removed the 10G Ethernet firmware from the kernel implementation and checked; Ethernet nodes are not detecting. Could you please guide us to resolve this issue? Here are the attached dmesg log and dtsi file for your reference.

root@j7200-iwg52m:~# devmem2 0x40F04040
/dev/mem opened.
Memory mapped at address 0xffff803ca000.
Read at address 0x40F04040 (0xffff803ca040): 0x00000001
root@j7200-iwg52m:~#
root@j7200-iwg52m:~#
root@j7200-iwg52m:~# devmem2 0x40F08050
/dev/mem opened.
Memory mapped at address 0xffffadb6d000.
Read at address 0x40F08050 (0xffffadb6d050): 0x00000F00
root@j7200-iwg52m:~#

root@j7200-iwg52m:~# cat /sys/kernel/debug/remoteproc/remoteproc*/trace0
Sciclient_boardCfgRm init Passed
DM Built On: Feb 28 2024 23:29:45
Sciserver Version: v2023.10.0.0-REL.PSDK.09.02.00.09-11-g14de0
RM_PM_HAL Version: v09.02.04
Starting Sciserver..... PASSED
IPC_echo_test (core : mcu1_0) .....
mcu1_0 <--> mcu1_1, Ping- 10000, pong - 10000 completed
mcu1_0 <--> mcu2_0, Ping- 10000, pong - 10000 completed
mcu1_0 <--> mcu2_1, Ping- 10000, pong - 10000 completed
IPC_echo_test (core : mcu1_1) .....
mcu1_1 <--> mcu1_0, Ping- 10000, pong - 10000 completed
mcu1_1 <--> mcu2_0, Ping- 10000, pong - 10000 completed
mcu1_1 <--> mcu2_1, Ping- 10000, pong - 10000 completed
IPC_echo_test (core : mcu2_0) .....
mcu2_0 <--> mcu2_1, Ping- 10000, pong - 10000 completed
mcu2_0 <--> mcu1_1, Ping- 10000, pong - 10000 completed
mcu2_0 <--> mcu1_0, Ping- 10000, pong - 10000 completed
IPC_echo_test (core : mcu2_1) .....
mcu2_1 <--> mcu2_0, Ping- 10000, pong - 10000 completed
mcu2_1 <--> mcu1_1, Ping- 10000, pong - 10000 completed
mcu2_1 <--> mcu1_0, Ping- 10000, pong - 10000 completed

Fullscreen k3-j7200-iwg52m-common-proc-board.txt Download

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2024-2025 iwave Global Technologies Pvt Ltd.
 */

/dts-v1/;

#include "k3-j7200-iwg52m.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>

/ {

	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};
        aliases {
                i2c0 = &wkup_i2c0;
                i2c1 = &mcu_i2c0;
		ethernet0 = &cpsw0_port3;
		ethernet1 = &cpsw0_port2;
		ethernet2 = &cpsw0_port1;
	};





	vdd_sd_dv: gpio-regulator-TLV71033 {
		/* Output of TLV71033 */
		compatible = "regulator-gpio";
		regulator-name = "tlv71033";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		gpios = <&wkup_gpio0 84 0>;
		gpios-states = <0>;
		states = <1800000 0x1>,
			 <3300000 0x0>;
	};
	iwg52m_info {
		compatible = "iwave,iwg52m-info";
	};
};

&wkup_pmx0 {
	b7_pins_default: b7-pins-default {
	pinctrl-single,pins = <
                J721E_WKUP_IOPAD(0x8, PIN_OUTPUT, 2) /* (B7)*/
		>;
	};

        som_eeprom_pins_default: som-eeprom-pins-default {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x24, PIN_INPUT, 7) /*A8 eeprom write protect gpio for Som*/
                >;
        };
	
	VU9p_pins_default_prog_pins_default: VU9p-pins-default-prog-pins-default {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x28, PIN_OUTPUT, 7) /*WKUP_GPIO0_26*/
                >;
        };

};


&wkup_pmx1 {

        d5_pins_default: d5-pins-default {
        pinctrl-single,pins = <
                J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 7) /* (D5)*/
                >;
        };
};
&wkup_pmx2 {
	mcu_uart0_pins_default: mcu-uart0-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
			J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
		>;
	};

	spi_pins_default: spi-pins-default {
		pinctrl-single,pins = <
		J721E_WKUP_IOPAD(0x58, PIN_INPUT, 0) /* (B18) WKUP_GPIO0_0.MCU_SPI1_CLK */
		J721E_WKUP_IOPAD(0x5c, PIN_OUTPUT, 0) /* (B19) WKUP_GPIO0_1.MCU_SPI1_D0 */
		J721E_WKUP_IOPAD(0x60, PIN_INPUT, 1) /* (D14) WKUP_GPIO0_2.MCU_SPI1_D1 */
		J721E_WKUP_IOPAD(0x06c, PIN_OUTPUT, 2) /* (B16) WKUP_GPIO0_5 TPM CS*/

		>;
	};

	vu_pmic2_pins_default: vu-pmic2-pins-default {
		pinctrl-single,pins = <
		J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /*A17*/
		>;
	};
	ps_gpio_header_uart_pins_default: ps-gpio-header-uart-pins-default {
		pinctrl-single,pins = <
		J721E_WKUP_IOPAD(0x90, PIN_INPUT, 7) /*E20*/
		J721E_WKUP_IOPAD(0x94, PIN_INPUT, 7) /*E21*/
		>;
	};
	
};

&wkup_pmx3 {
      	 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
                pinctrl-single,pins = <
                	J721E_WKUP_IOPAD(0x1C, PIN_OUTPUT, 7) /*E18 */
		>;
        };
};

&main_pmx0 {
	main_uart0_pins_default: main-uart0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
			J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
		>;
	};

	VU9p_pins_default_done: VU9p-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0xd8, PIN_INPUT, 7) /* (W2) MAIN_GPIO0_57 */
		>;
	};

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
			J721E_IOPAD(0x100, PIN_OUTPUT, 0) /* (P21) MMC1_CLK */
			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
		>;
	};

	main_cpsw_pins_default: main-cpsw-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x4c, PIN_INPUT, 4) /* (V19) MCAN5_RX.RGMII3_RD0 */
			J721E_IOPAD(0x50, PIN_INPUT, 4) /* (T13) MCAN6_TX.RGMII3_RD1 */
			J721E_IOPAD(0x54, PIN_INPUT, 4) /* (U14) MCAN6_RX.RGMII3_RD2 */
			J721E_IOPAD(0x58, PIN_INPUT, 4) /* (U16) MCAN7_TX.RGMII3_RD3 */
			J721E_IOPAD(0x48, PIN_INPUT, 4) /* (V21) MCAN5_TX.RGMII3_RXC */
			J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (U15) MCAN7_RX.RGMII3_RX_CTL */
			J721E_IOPAD(0x60, PIN_OUTPUT, 4) /* (T15) MCAN8_TX.RGMII3_TD0 */
			J721E_IOPAD(0x64, PIN_OUTPUT, 4) /* (U19) MCAN8_RX.RGMII3_TD1 */
			J721E_IOPAD(0x68, PIN_OUTPUT, 4) /* (T14) MCAN9_TX.RGMII3_TD2 */
			J721E_IOPAD(0x6c, PIN_OUTPUT, 4) /* (U18) MCAN9_RX.RGMII3_TD3 */
			J721E_IOPAD(0x74, PIN_OUTPUT, 4) /* (U20) MCAN10_RX.RGMII3_TXC */
			J721E_IOPAD(0x70, PIN_OUTPUT, 4) /* (U17) MCAN10_TX.RGMII3_TX_CTL */
		>;
	};
	main_mdio_pins_default: main-mdio1-pins-default{
		pinctrl-single,pins = <
			J721E_IOPAD(0xa8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
			J721E_IOPAD(0xa4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
		>;
	};

	eth_reset_pins_default: gpio0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0xd4, PIN_INPUT, 7) /* (V3) I2C0_SCL.GPIO0_56 */
		>;
	};
	Eth_10G_reset_pins_default: Eth-10G-reset-pins-default {
                pinctrl-single,pins = <
                        J721E_IOPAD(0xE0, PIN_INPUT, 7) /* (T3)*/
                >;
        };

	typec_irq_pins_default: typec-irq-pins-default {
		pinctrl-single,pins = <
                J721E_IOPAD(0xc4, PIN_INPUT_PULLUP, 7) /* (U5) MAIN_GPIO0_52 */
                >;
        };

	vu_pmic1_pins_default: vu-pmic1-pins-default {
		pinctrl-single,pins = < 
			J721E_IOPAD(0x1c, PIN_OUTPUT, 7) /*AA19*/
		>;
	};

	RGMII2_pins_default: RGMII2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x28, PIN_OUTPUT, 4) /*(W21) RGMII2_TXC/MCAN1_TX/RMII2_TX_EN/SPI6_CS0/EHRPWM_SOCA/GPMC0_A3/MCASP0_AXR11/GPIO0_11*/
			J721E_IOPAD(0xa0, PIN_OUTPUT, 4) /*(U21) RGMII2_TX_CTL/GPIO0_41/RMII2_TXD0/SPI6_D1/UART4_RXD/GPMC0_A13/MCASP2_ACLKX */
			J721E_IOPAD(0x90, PIN_OUTPUT, 4) /*(W17) RGMII2_TD0/MCAN15_TX/RMII2_RXD0/GPIO0_37/SPI6_CS2/EQEP1_S/GPMC0_CSN2/GPMC0_A0/GPMC0_A21/MCASP2_AXR1*/
			J721E_IOPAD(0x94, PIN_OUTPUT, 4) /*(W20) RGMII2_TD1/MCAN15_RX/RMII2_RXD1/SPI6_CS3/EQEP1_I/GPMC0_A15/GPMC0_ADVN_ALE/GPIO0_38/MCASP2_AXR2 */
			J721E_IOPAD(0x98, PIN_OUTPUT, 4) /*(V14) RGMII2_TD2/UART2_RXD/RMII2_CRS_DV/SPI6_CLK/GPMC0_CLKOUT/GPMC0_FCLK_MUX/OBSCLK2/GPIO0_39/MCASP2_AXR3*/
			J721E_IOPAD(0x9c, PIN_OUTPUT, 4) /*(V13) RGMII2_TD3/UART2_TXD/RMII2_RX_ER/GPIO0_40/SPI6_D0/MCASP2_AFSX */
			J721E_IOPAD(0x78, PIN_INPUT, 4) /*(Y14)  RGMII2_RXC/MCAN11_TX/SPI2_CS0/EQEP0_A/SPI0_CS2/UART3_RXD/MCASP0_AXR13/GPMC0_A11/UART0_DTRN/GPIO0_31*/
			J721E_IOPAD(0x8c, PIN_INPUT, 4) /*(AA16) RGMII2_RX_CTL/MCAN13_RX/GPMC0_CSN3/GPIO0_36/SPI2_D1/EQEP0_I/I2C5_SDA/UART8_RTSN/I3C0_SDA/GPMC0_A20/MCASP2_AXR0 */
			J721E_IOPAD(0x7c, PIN_INPUT, 4) /*(Y13)  RGMII2_RD0/MCAN11_RX/SPI2_CS1/EQEP0_B/UART3_TXD/MCASP0_AXR14/GPMC0_A12/UART0_RIN/GPIO0_32 */
			J721E_IOPAD(0x80, PIN_INPUT, 4) /*(AA15) RGMII2_RD1/GPIO0_33/SPI2_CS2/EQEP1_A/I2C6_SCL/UART2_RXD/MCASP0_AXR15/GPMC0_BE1N/GPMC0_A17/MCAN12_TX */
			J721E_IOPAD(0x84, PIN_INPUT, 4) /*(AA14) RGMII2_RD2/GPIO0_34/SPI2_CS3/EQEP1_B/I2C6_SDA/UART2_TXD/MCASP1_AXR8/I3C0_SDAPULLEN/GPMC0_A18/MCAN12_RX */
			J721E_IOPAD(0x88, PIN_INPUT, 4) /*(AA18) RGMII2_RD3/MCAN13_TX/GPMC0_WPN/SPI2_D0/EQEP0_S/I2C5_SCL/UART8_CTSN/MCASP1_AXR9/I3C0_SCL/GPMC0_A19/GPIO0_35 */
		>;
	};

	main_uart1_pins_default: main-uart1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0xbc, PIN_OUTPUT, 0) /* (T20) UART1_TXD.MCAN17_RX */
			J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD.MCAN17_TX */
		>;
	};
	pcie_rst_pins_default: pcie-rst-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x44, PIN_INPUT, 7) /*Y20*/
		>;
	};
	ps_gpio_header_pins_default: ps-gpio-header-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x20, PIN_INPUT, 7) /* (V18) MCAN0_TX.GPIO0_9 */
			J721E_IOPAD(0x24, PIN_INPUT, 7) /* (V20) MCAN0_RX.GPIO0_10 */
			J721E_IOPAD(0x38, PIN_INPUT, 7) /* (Y21) MCAN3_TX.GPIO0_15 */
			J721E_IOPAD(0x3c, PIN_INPUT, 7) /* (W16) MCAN3_RX.GPIO0_16 */
		>;
	};
	tpm_reset_pins_default: tpm-reset-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0c0, PIN_OUTPUT_PULLUP, 7)
		>;
	};
};

&main_pmx2 {
	main_usbss0_pins_default: main-usbss0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
		>;
	};
};

&mcu_uart0 {
	status = "okay";
	/* Default pinmux */
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_uart0_pins_default>;
};

&main_uart0 {
	status = "okay";
	/* Shared with ATF on this platform */
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
};

&main_uart1 {
	status = "okay";
	/* Default pinmux */
        pinctrl-names = "default";
        pinctrl-0 = <&main_uart1_pins_default>;

};

&main_uart2 {
	/* MAIN UART 2 is used by R5F firmware */
	status = "reserved";
};


&main_gpio0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&eth_reset_pins_default &Eth_10G_reset_pins_default &ps_gpio_header_pins_default &VU9p_pins_default_done &tpm_reset_pins_default>;
	10G_reset_gpio {
		gpio-hog;
		gpios = <59 GPIO_ACTIVE_HIGH>;
		output-high;
		linename = "10G_rst";
	};
};

&main_gpio2 {
	status = "disabled";
};

&main_gpio4 {
	status = "disabled";
};

&main_gpio6 {
	status = "disabled";
};

&wkup_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ps_gpio_header_uart_pins_default &VU9p_pins_default_prog_pins_default>;
};

&wkup_gpio1 {
	status = "disabled";
};

&cpsw0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_cpsw_pins_default &RGMII2_pins_default>;

};

&davinci_mdio{

	status = "disabled";
	
};

&mcu_cpsw{
	status = "disabled";
};

&cpsw_port1 {
	status = "disabled";
};

&cpsw5g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mdio_pins_default>;
	
	phy3: ethernet-phy@3 {
		reg = <3>;
		compatible = "ethernet-phy-ieee802.3-c22";
	};
        phy1: ethernet-phy@1 {
                reg = <1>;
		compatible = "ethernet-phy-ieee802.3-c45";
		device_type = "ethernet-phy";
		host-in-si1;
        };

};


&cpsw0_port3 {
	status = "okay";
	pinctrl-names = "default";
	phy-mode = "rgmii-id";
	phy-handle = <&phy3>;
	phys = <&cpsw0_phy_gmii_sel 3>;
};

&cpsw0_port1 {
	status = "okay";
	phy-mode = "usxgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 1>, <&serdes0_usxgmii_link>;
	phy-names = "mac", "serdes";
	fixed-link {
		speed = <10000>;
		full-duplex;
	};
};

&cpsw0_port2 {
	status = "okay";
	phy-mode = "rgmii";
	phys = <&cpsw0_phy_gmii_sel 2>;
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&main_i2c0 {
	status = "disabled";
};
&wkup_i2c0 {
	status = "okay";
	clock-frequency = <400000>;
                eeprom_osm: eeprom@54 {
                        status = "okay";
                        compatible = "atmel,24mac402";
                        reg = <0x54>;
                        pagesize = <16>;
                        address-width = <8>;
                        size = <256>;
                };
	        i2c_mux: msd9548@73 {
                compatible = "nxp,pca9548";
                reg = <0x73>;
                status = "okay";
                #address-cells = <1>;
                #size-cells = <0>;
                i2c@0 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0>;
                };
                i2c@1{
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <1>;
                        ioexp3gpio: gpio@20 {
                                compatible = "ti,tca6416";
                                reg = <0x20>;
                                #gpio-cells = <2>;
                                gpio-controller;
				#interrupt-cells = <2>;
                               	interrupt-controller;
				interrupt-parent = <&ioexp2gpio>;
				interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
				label = "ioexp3gpio";
                                usb_power{
                                        gpio-hog;
                                        gpios = <12 GPIO_ACTIVE_HIGH>;
                                        output-high;
                                };
                        };
                };
		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			};
		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			};
		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			};
		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
			};
		i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
			};
                i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
                        reg = <7>;
			ioexp1gpio: gpio@21 {
				compatible = "ti,tca6416";
				reg = <0x21>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&main_gpio0>;
				interrupts = <52 IRQ_TYPE_EDGE_FALLING>;
				label = "ioexp1gpio";
				qsfp_1_top {
					gpio-hog;
					gpios = <0 0>;
					output-low;
				};
				qsfp_1_bottom {
                                        gpio-hog;
                                        gpios = <5 0>;
                                        output-low;
                                };
			};
			ioexp2gpio: gpio@20 {
				compatible = "ti,tca6416";
				reg = <0x20>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-parent = <&ioexp1gpio>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
				label = "ioexp2gpio";
                                qsfp_2_top {
                                        gpio-hog;
                                        gpios = <0 0>;
                                        output-low;
                                };
                                qsfp_2_bottom {
                                        gpio-hog;
                                        gpios = <5 0>;
                                        output-low;
                                };
			};
			fusb302: typec-portc@22 {
				compatible = "fcs,fusb302";
				pinctrl-names = "default";
				pinctrl-0 = <&typec_irq_pins_default>;
				reg = <0x22>;
				fcs,int_n = <&ioexp3gpio 15 IRQ_TYPE_EDGE_FALLING>;
				status = "okay";
			};
			dp159: hdmi-retimer@5b {
				status = "okay";
				compatible = "ti,dp159";
				reg = <0x5b>;
				#address-cells = <1>;
				#size-cells = <0>;
				#clock-cells = <0>;
			};
                };
        };
};

&mcu_i2c0 {
	status = "okay";
	clock-frequency = <400000>;

	tmp442@4c {
		compatible = "ti,tmp442";
		reg = <0x4c>;
	};
        eeprom_som: eeprom@52 {
		pinctrl-names = "default";
		pinctrl-0 = <&som_eeprom_pins_default>;
                status = "okay";
                compatible = "atmel,24mac402";
                reg = <0x52>;
                pagesize = <16>;
                address-width = <8>;
                size = <256>;
        };
        eeprom_Carrier_board: eeprom@50 {
                compatible = "atmel,24c04";
                reg = <0x50>;
                pagesize = <16>;
                address-width = <8>;
                size = <512>;
        };



	vu09_pmic_1: vu09_da9062@48 {
		compatible = "dlg,da9062";
		pinctrl-names = "default";
		pinctrl-0 = <&vu_pmic1_pins_default>;
		reg = <0x48>;
		gpio-controller;
		#gpio-cells = <2>;
		status = "okay";
		
		gpio {
                        compatible = "dlg,da9062-gpio";
                };
	};

        vu09_pmic_2: vu09_da9062@58 {
                compatible = "dlg,da9062";
                pinctrl-names = "default";
                pinctrl-0 = <&vu_pmic2_pins_default>;
                reg = <0x58>;
                gpio-controller;
                #gpio-cells = <2>;
                status = "okay";

                gpio {
                        compatible = "dlg,da9062-gpio";
                };
        };

		

};
&mcu_i2c1 {

	status = "disabled";
};

&main_sdhci0 {
	status = "okay";
	/* eMMC */
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	status = "okay";
	/* SD card */
	pinctrl-0 = <&main_mmc1_pins_default>;
	pinctrl-names = "default";
	vqmmc-supply = <&vdd_sd_dv>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	bus-width = <4>;
};

&serdes_ln_ctrl {
	status = "okay";
	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
};


&usb_serdes_mux {
	idle-states = <1>; /* USB0 to SERDES lane 3 */
};

&usbss0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss0_pins_default>;
	ti,vbus-divider;
	ti,usb2-only;
};

&usb0 {
	status = "okay";
	dr_mode = "host";
        phy-names = "cdns3,usb2-phy";
};

&tscadc0 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&serdes_refclk {
	clock-frequency = <100000000>;
};


&serdes_wiz0 {
	status = "okay";
};
&serdes0 {
	status = "okay";
	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
	};

	serdes0_usxgmii_link: phy@1 {
		reg = <2>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USXGMII>;
		resets = <&serdes_wiz0 3>;
	};
};

&pcie1_rc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_rst_pins_default>;
	reset-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>;
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
};



#define K3_TS_OFFSET(pa, val)  (0x4+(pa)*4) (0x10000 | val)

&timesync_router {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_cpts>;

	/* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */
	mcu_cpsw_cpts: mcu-cpsw-cpts {
		pinctrl-single,pins = <
			/* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */
			K3_TS_OFFSET(25, 17)
			>;
	};
};

&mcu_spi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi_pins_default>;
	ti,spi-num-cs = <4>;
	ti,pindir-d0-out-d1-in;
	tpm@3 {
		compatible = "tcg,tpm_tis-spi";
		reg = <3>;
		spi-max-frequency = <16000000>;
		lpcpd-gpios = <&main_gpio0 51 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};
};

Thanks and Regards,
Subashini

0 Doredla Sudheer Kumar 2 months ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Let me check on my side with same configuraiton and get back to you.

Best Regards,
Sudheer

0 Subashini N 2 months ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

Hope you are doing well. Did you get any chance to look into this? Could you please provide any updates on this?

Thanks and Regards,

Subashini

0 Doredla Sudheer Kumar 2 months ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Sorry I am still checking on this, and get back to you soon.

Best Regards,
Sudheer

0 Subashini N 2 months ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

The following header file doesn't have the USXGMII entry; how can I add an entry for this? I am using the SDK version: 09_02_00_04.

include/dt-bindings/mux/ti-serdes.h

Thanks and Regards,
Subashini

0 Doredla Sudheer Kumar 2 months ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Subashini N said:
The following header file doesn't have the USXGMII entry; how can I add an entry for this? I am using the SDK version: 09_02_00_04.

include/dt-bindings/mux/ti-serdes.h

This is for selection of an IP instance from SerDes lanes.
You can still use "J7200_SERDES0_LANE2_QSGMII_LANE1", which makes SerDes Lane2 as CPSW feature.

Interface selection is based on "cdns,phy-type" property in serdes node.

Best Regards,
Sudheer

0 Subashini N 2 months ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

In the SerDes lane, I kept J7200_SERDES0_LANE2_QSGMII_LANE1, and for the 10G Ethernet node, I added cdns,phy-type = <PHY_TYPE_USXGMII>; as the phy type. While booting, I am getting unknown PHY type and timeout issues.

root@j7200-iwg52m:~#
root@j7200-iwg52m:~# dmesg | grep -i phy
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.656832] phy-gmii-sel 40f04040.phy: phy_gmii_sel_init_ports 1
[    0.656841] phy-gmii-sel 40f04040.phy: phy_gmii_init_phy field 4040 2 0
[    0.657006] phy-gmii-sel 104044.phy: phy_gmii_sel_init_ports 4
[    0.657011] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 4044 2 0
[    0.657042] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 4048 2 0
[    0.657069] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 404c 2 0
[    0.657094] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 4050 2 0
[    1.089775] wiz bus@100000:wiz@5060000: wiz_get_lane_phy_types: Lanes 0-1 have phy-type 2
[    1.089781] wiz bus@100000:wiz@5060000: wiz_get_lane_phy_types: Lanes 2-2 have phy-type 12
[    1.273977] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[    1.273991] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[    1.290580] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[    1.290596] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[    1.290701] davinci_mdio c000f00.mdio: phy[1]: device c000f00.mdio:01, driver unknown
[    1.300476] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F-VD-CG Gigabit Ethernet
[    1.328728] phy-gmii-sel 104044.phy: phy_gmii_sel_of_xlate id:1 ext:139780496
[    2.169367] cdns-torrent-phy 5060000.serdes: Timeout waiting for CMN ready
[    2.177975] phy phy-5060000.serdes.5: phy poweron failed --> -110
[    2.185596] j721e-pcie-host 2910000.pcie: Failed to init phy
[    2.304347] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[    2.304393] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[    2.323192] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[    2.323206] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[    2.323356] davinci_mdio c000f00.mdio: phy[1]: device c000f00.mdio:01, driver unknown
[    2.333154] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F-VD-CG Gigabit Ethernet
[    2.361471] phy-gmii-sel 104044.phy: phy_gmii_sel_of_xlate id:1 ext:139780496
[    2.462245] cdns-torrent-phy 5060000.serdes: Timeout waiting for CMN ready
[    2.470852] phy phy-5060000.serdes.6: phy poweron failed --> -110

root@j7200-iwg52m:~# dmesg | grep -i eth
[    0.000000] psci: probing for conduit method from DT.
[    0.811187] optee: probing for conduit method.
[    1.224096] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00[0]'
[    1.224107] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00[0]'
[    1.273977] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[    1.273991] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[    1.290580] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[    1.290596] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[    1.300476] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F-VD-CG Gigabit Ethernet
[    1.312871] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 5 quirks:00000000
[    2.240049] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00[0]'
[    2.240070] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00[0]'
[    2.304347] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[    2.304393] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[    2.323192] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[    2.323206] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[    2.333154] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F-VD-CG Gigabit Ethernet
[    2.345586] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 5 quirks:00000000
[    2.479365] am65-cpsw-nuss: probe of c000000.ethernet failed with error -110
[    4.020626] systemd[1]: /lib/systemd/system/bt-enable.service:9: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the sett.
[    4.081283] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the s.
root@j7200-iwg52m:~#

Thanks and Regards,
Subashini

0 Doredla Sudheer Kumar 1 month ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Subashini N said:
[ 1.290596] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 1.290701] davinci_mdio c000f00.mdio: phy[1]: device c000f00.mdio:01, driver unknown

Which PHY is connected at Address 1?
I can see PHY3 is mapped to CPSW MAC Port, PHY 1 is not mapped to any node?

For un-known PHY, can you please check whether you have USXGMII flags under extra modes?

Can you please check with latest TI SDK?

Best Regards,
Sudheer

0 Subashini N 1 month ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

HI Sudheer,

I have checked both drivers, and both contain the USXGMII flag entry. Also, I connected phy1 to the 10G node, but I am still seeing the “unknown device” and timeout issues.

I am currently using SDK version 09_02_00_04. Does this SDK version support 10G implementation? If it does, could you please guide us on implementing 10G on our custom DRA821U board using this SDK version?

Our board supports both x2 PCIe and 10G interfaces. We are using the Marvell 10G PHY (88X3310-A1-BUS4I000) on our board.

I have also attached the Marvell driver changes. Can I keep those changes, or are any modifications required? Please confirm.

Additionally, I have attached the DTSI files and driver change images for your reference.

Fullscreen 2671.dts.txt Download

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2024-2025 iwave Global Technologies Pvt Ltd.
 */

/dts-v1/;

#include "k3-j7200-iwg52m.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>

/ {

	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};
        aliases {
                i2c0 = &wkup_i2c0;
                i2c1 = &mcu_i2c0;
		ethernet0 = &cpsw0_port3;
		ethernet1 = &cpsw0_port2;
		ethernet2 = &cpsw0_port1;
	};





	vdd_sd_dv: gpio-regulator-TLV71033 {
		/* Output of TLV71033 */
		compatible = "regulator-gpio";
		regulator-name = "tlv71033";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		gpios = <&wkup_gpio0 84 0>;
		gpios-states = <0>;
		states = <1800000 0x1>,
			 <3300000 0x0>;
	};
	iwg52m_info {
		compatible = "iwave,iwg52m-info";
	};
};

&wkup_pmx0 {
	b7_pins_default: b7-pins-default {
	pinctrl-single,pins = <
                J721E_WKUP_IOPAD(0x8, PIN_OUTPUT, 2) /* (B7)*/
		>;
	};

        som_eeprom_pins_default: som-eeprom-pins-default {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x24, PIN_INPUT, 7) /*A8 eeprom write protect gpio for Som*/
                >;
        };
	
	VU9p_pins_default_prog_pins_default: VU9p-pins-default-prog-pins-default {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x28, PIN_OUTPUT, 7) /*WKUP_GPIO0_26*/
                >;
        };

};


&wkup_pmx1 {

        d5_pins_default: d5-pins-default {
        pinctrl-single,pins = <
                J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 7) /* (D5)*/
                >;
        };
};
&wkup_pmx2 {
	mcu_uart0_pins_default: mcu-uart0-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
			J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
		>;
	};

	spi_pins_default: spi-pins-default {
		pinctrl-single,pins = <
		J721E_WKUP_IOPAD(0x58, PIN_INPUT, 0) /* (B18) WKUP_GPIO0_0.MCU_SPI1_CLK */
		J721E_WKUP_IOPAD(0x5c, PIN_OUTPUT, 0) /* (B19) WKUP_GPIO0_1.MCU_SPI1_D0 */
		J721E_WKUP_IOPAD(0x60, PIN_INPUT, 1) /* (D14) WKUP_GPIO0_2.MCU_SPI1_D1 */
		J721E_WKUP_IOPAD(0x06c, PIN_OUTPUT, 2) /* (B16) WKUP_GPIO0_5 TPM CS*/

		>;
	};

	vu_pmic2_pins_default: vu-pmic2-pins-default {
		pinctrl-single,pins = <
		J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /*A17*/
		>;
	};
	ps_gpio_header_uart_pins_default: ps-gpio-header-uart-pins-default {
		pinctrl-single,pins = <
		J721E_WKUP_IOPAD(0x90, PIN_INPUT, 7) /*E20*/
		J721E_WKUP_IOPAD(0x94, PIN_INPUT, 7) /*E21*/
		>;
	};
	
};

&wkup_pmx3 {
      	 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
                pinctrl-single,pins = <
                	J721E_WKUP_IOPAD(0x1C, PIN_OUTPUT, 7) /*E18 */
		>;
        };
};

&main_pmx0 {
	main_uart0_pins_default: main-uart0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
			J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
		>;
	};

	VU9p_pins_default_done: VU9p-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0xd8, PIN_INPUT, 7) /* (W2) MAIN_GPIO0_57 */
		>;
	};

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
			J721E_IOPAD(0x100, PIN_OUTPUT, 0) /* (P21) MMC1_CLK */
			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
		>;
	};

	main_cpsw_pins_default: main-cpsw-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x4c, PIN_INPUT, 4) /* (V19) MCAN5_RX.RGMII3_RD0 */
			J721E_IOPAD(0x50, PIN_INPUT, 4) /* (T13) MCAN6_TX.RGMII3_RD1 */
			J721E_IOPAD(0x54, PIN_INPUT, 4) /* (U14) MCAN6_RX.RGMII3_RD2 */
			J721E_IOPAD(0x58, PIN_INPUT, 4) /* (U16) MCAN7_TX.RGMII3_RD3 */
			J721E_IOPAD(0x48, PIN_INPUT, 4) /* (V21) MCAN5_TX.RGMII3_RXC */
			J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (U15) MCAN7_RX.RGMII3_RX_CTL */
			J721E_IOPAD(0x60, PIN_OUTPUT, 4) /* (T15) MCAN8_TX.RGMII3_TD0 */
			J721E_IOPAD(0x64, PIN_OUTPUT, 4) /* (U19) MCAN8_RX.RGMII3_TD1 */
			J721E_IOPAD(0x68, PIN_OUTPUT, 4) /* (T14) MCAN9_TX.RGMII3_TD2 */
			J721E_IOPAD(0x6c, PIN_OUTPUT, 4) /* (U18) MCAN9_RX.RGMII3_TD3 */
			J721E_IOPAD(0x74, PIN_OUTPUT, 4) /* (U20) MCAN10_RX.RGMII3_TXC */
			J721E_IOPAD(0x70, PIN_OUTPUT, 4) /* (U17) MCAN10_TX.RGMII3_TX_CTL */
		>;
	};
	main_mdio_pins_default: main-mdio1-pins-default{
		pinctrl-single,pins = <
			J721E_IOPAD(0xa8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
			J721E_IOPAD(0xa4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
		>;
	};

	eth_reset_pins_default: gpio0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0xd4, PIN_INPUT, 7) /* (V3) I2C0_SCL.GPIO0_56 */
		>;
	};
	Eth_10G_reset_pins_default: Eth-10G-reset-pins-default {
                pinctrl-single,pins = <
                        J721E_IOPAD(0xE0, PIN_INPUT, 7) /* (T3)*/
                >;
        };

	typec_irq_pins_default: typec-irq-pins-default {
		pinctrl-single,pins = <
                J721E_IOPAD(0xc4, PIN_INPUT_PULLUP, 7) /* (U5) MAIN_GPIO0_52 */
                >;
        };

	vu_pmic1_pins_default: vu-pmic1-pins-default {
		pinctrl-single,pins = < 
			J721E_IOPAD(0x1c, PIN_OUTPUT, 7) /*AA19*/
		>;
	};

	RGMII2_pins_default: RGMII2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x28, PIN_OUTPUT, 4) /*(W21) RGMII2_TXC/MCAN1_TX/RMII2_TX_EN/SPI6_CS0/EHRPWM_SOCA/GPMC0_A3/MCASP0_AXR11/GPIO0_11*/
			J721E_IOPAD(0xa0, PIN_OUTPUT, 4) /*(U21) RGMII2_TX_CTL/GPIO0_41/RMII2_TXD0/SPI6_D1/UART4_RXD/GPMC0_A13/MCASP2_ACLKX */
			J721E_IOPAD(0x90, PIN_OUTPUT, 4) /*(W17) RGMII2_TD0/MCAN15_TX/RMII2_RXD0/GPIO0_37/SPI6_CS2/EQEP1_S/GPMC0_CSN2/GPMC0_A0/GPMC0_A21/MCASP2_AXR1*/
			J721E_IOPAD(0x94, PIN_OUTPUT, 4) /*(W20) RGMII2_TD1/MCAN15_RX/RMII2_RXD1/SPI6_CS3/EQEP1_I/GPMC0_A15/GPMC0_ADVN_ALE/GPIO0_38/MCASP2_AXR2 */
			J721E_IOPAD(0x98, PIN_OUTPUT, 4) /*(V14) RGMII2_TD2/UART2_RXD/RMII2_CRS_DV/SPI6_CLK/GPMC0_CLKOUT/GPMC0_FCLK_MUX/OBSCLK2/GPIO0_39/MCASP2_AXR3*/
			J721E_IOPAD(0x9c, PIN_OUTPUT, 4) /*(V13) RGMII2_TD3/UART2_TXD/RMII2_RX_ER/GPIO0_40/SPI6_D0/MCASP2_AFSX */
			J721E_IOPAD(0x78, PIN_INPUT, 4) /*(Y14)  RGMII2_RXC/MCAN11_TX/SPI2_CS0/EQEP0_A/SPI0_CS2/UART3_RXD/MCASP0_AXR13/GPMC0_A11/UART0_DTRN/GPIO0_31*/
			J721E_IOPAD(0x8c, PIN_INPUT, 4) /*(AA16) RGMII2_RX_CTL/MCAN13_RX/GPMC0_CSN3/GPIO0_36/SPI2_D1/EQEP0_I/I2C5_SDA/UART8_RTSN/I3C0_SDA/GPMC0_A20/MCASP2_AXR0 */
			J721E_IOPAD(0x7c, PIN_INPUT, 4) /*(Y13)  RGMII2_RD0/MCAN11_RX/SPI2_CS1/EQEP0_B/UART3_TXD/MCASP0_AXR14/GPMC0_A12/UART0_RIN/GPIO0_32 */
			J721E_IOPAD(0x80, PIN_INPUT, 4) /*(AA15) RGMII2_RD1/GPIO0_33/SPI2_CS2/EQEP1_A/I2C6_SCL/UART2_RXD/MCASP0_AXR15/GPMC0_BE1N/GPMC0_A17/MCAN12_TX */
			J721E_IOPAD(0x84, PIN_INPUT, 4) /*(AA14) RGMII2_RD2/GPIO0_34/SPI2_CS3/EQEP1_B/I2C6_SDA/UART2_TXD/MCASP1_AXR8/I3C0_SDAPULLEN/GPMC0_A18/MCAN12_RX */
			J721E_IOPAD(0x88, PIN_INPUT, 4) /*(AA18) RGMII2_RD3/MCAN13_TX/GPMC0_WPN/SPI2_D0/EQEP0_S/I2C5_SCL/UART8_CTSN/MCASP1_AXR9/I3C0_SCL/GPMC0_A19/GPIO0_35 */
		>;
	};

	main_uart1_pins_default: main-uart1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0xbc, PIN_OUTPUT, 0) /* (T20) UART1_TXD.MCAN17_RX */
			J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD.MCAN17_TX */
		>;
	};
	pcie_rst_pins_default: pcie-rst-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x44, PIN_OUTPUT, 7) /*Y20*/
		>;
	};
	ps_gpio_header_pins_default: ps-gpio-header-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x20, PIN_INPUT, 7) /* (V18) MCAN0_TX.GPIO0_9 */
			J721E_IOPAD(0x24, PIN_INPUT, 7) /* (V20) MCAN0_RX.GPIO0_10 */
			J721E_IOPAD(0x38, PIN_INPUT, 7) /* (Y21) MCAN3_TX.GPIO0_15 */
			J721E_IOPAD(0x3c, PIN_INPUT, 7) /* (W16) MCAN3_RX.GPIO0_16 */
		>;
	};
	tpm_reset_pins_default: tpm-reset-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0c0, PIN_OUTPUT_PULLUP, 7)
		>;
	};
};

&main_pmx2 {
	main_usbss0_pins_default: main-usbss0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
		>;
	};
};

&mcu_uart0 {
	status = "okay";
	/* Default pinmux */
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_uart0_pins_default>;
};

&main_uart0 {
	status = "okay";
	/* Shared with ATF on this platform */
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
};

&main_uart1 {
	status = "okay";
	/* Default pinmux */
        pinctrl-names = "default";
        pinctrl-0 = <&main_uart1_pins_default>;

};

&main_uart2 {
	/* MAIN UART 2 is used by R5F firmware */
	status = "reserved";
};


&main_gpio0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&eth_reset_pins_default &Eth_10G_reset_pins_default &ps_gpio_header_pins_default &VU9p_pins_default_done &tpm_reset_pins_default>;
	10G_reset_gpio {
		gpio-hog;
		gpios = <59 GPIO_ACTIVE_HIGH>;
		output-high;
		linename = "10G_rst";
	};
};

&main_gpio2 {
	status = "disabled";
};

&main_gpio4 {
	status = "disabled";
};

&main_gpio6 {
	status = "disabled";
};

&wkup_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ps_gpio_header_uart_pins_default &VU9p_pins_default_prog_pins_default>;
};

&wkup_gpio1 {
	status = "disabled";
};

&cpsw0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_cpsw_pins_default &RGMII2_pins_default>;

};

&davinci_mdio{

	status = "disabled";
	
};

&mcu_cpsw{
	status = "disabled";
};

&cpsw_port1 {
	status = "disabled";
};

&cpsw5g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mdio_pins_default>;
	
	phy3: ethernet-phy@3 {
		reg = <3>;
		compatible = "ethernet-phy-ieee802.3-c22";
	};
        phy1: ethernet-phy@1 {
                reg = <1>;
		compatible = "ethernet-phy-ieee802.3-c45";
        };

};


&cpsw0_port3 {
	status = "okay";
	pinctrl-names = "default";
	phy-mode = "rgmii-id";
	phy-handle = <&phy3>;
	phys = <&cpsw0_phy_gmii_sel 3>;
};

&cpsw0_port1 {
	status = "okay";
	phy-mode = "usxgmii";
	phys = <&cpsw0_phy_gmii_sel 1>, <&serdes0_usxgmii_link>;
	phy-names = "mac", "serdes";
	phy-handle = <&phy1>;
};

&cpsw0_port2 {
	status = "okay";
	phy-mode = "rgmii";
	phys = <&cpsw0_phy_gmii_sel 2>;
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&main_i2c0 {
	status = "disabled";
};
&wkup_i2c0 {
	status = "okay";
	clock-frequency = <400000>;
                eeprom_osm: eeprom@54 {
                        status = "okay";
                        compatible = "atmel,24mac402";
                        reg = <0x54>;
                        pagesize = <16>;
                        address-width = <8>;
                        size = <256>;
                };
	        i2c_mux: msd9548@73 {
                compatible = "nxp,pca9548";
                reg = <0x73>;
                status = "okay";
                #address-cells = <1>;
                #size-cells = <0>;
                i2c@0 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0>;
                };
                i2c@1{
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <1>;
                        ioexp3gpio: gpio@20 {
                                compatible = "ti,tca6416";
                                reg = <0x20>;
                                #gpio-cells = <2>;
                                gpio-controller;
				#interrupt-cells = <2>;
                               	interrupt-controller;
				interrupt-parent = <&ioexp2gpio>;
				interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
				label = "ioexp3gpio";
                                usb_power{
                                        gpio-hog;
                                        gpios = <12 GPIO_ACTIVE_HIGH>;
                                        output-high;
                                };
                        };
                };
		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			};
		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			};
		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			};
		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
			};
		i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
			};
                i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
                        reg = <7>;
			ioexp1gpio: gpio@21 {
				compatible = "ti,tca6416";
				reg = <0x21>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&main_gpio0>;
				interrupts = <52 IRQ_TYPE_EDGE_FALLING>;
				label = "ioexp1gpio";
				qsfp_1_top {
					gpio-hog;
					gpios = <0 0>;
					output-low;
				};
				qsfp_1_bottom {
                                        gpio-hog;
                                        gpios = <5 0>;
                                        output-low;
                                };
			};
			ioexp2gpio: gpio@20 {
				compatible = "ti,tca6416";
				reg = <0x20>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-parent = <&ioexp1gpio>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
				label = "ioexp2gpio";
                                qsfp_2_top {
                                        gpio-hog;
                                        gpios = <0 0>;
                                        output-low;
                                };
                                qsfp_2_bottom {
                                        gpio-hog;
                                        gpios = <5 0>;
                                        output-low;
                                };
			};
			fusb302: typec-portc@22 {
				compatible = "fcs,fusb302";
				pinctrl-names = "default";
				pinctrl-0 = <&typec_irq_pins_default>;
				reg = <0x22>;
				fcs,int_n = <&ioexp3gpio 15 IRQ_TYPE_EDGE_FALLING>;
				status = "okay";
			};
			dp159: hdmi-retimer@5b {
				status = "okay";
				compatible = "ti,dp159";
				reg = <0x5b>;
				#address-cells = <1>;
				#size-cells = <0>;
				#clock-cells = <0>;
			};
                };
        };
};

&mcu_i2c0 {
	status = "okay";
	clock-frequency = <400000>;

	tmp442@4c {
		compatible = "ti,tmp442";
		reg = <0x4c>;
	};
        eeprom_som: eeprom@52 {
		pinctrl-names = "default";
		pinctrl-0 = <&som_eeprom_pins_default>;
                status = "okay";
                compatible = "atmel,24mac402";
                reg = <0x52>;
                pagesize = <16>;
                address-width = <8>;
                size = <256>;
        };
        eeprom_Carrier_board: eeprom@50 {
                compatible = "atmel,24c04";
                reg = <0x50>;
                pagesize = <16>;
                address-width = <8>;
                size = <512>;
        };



	vu09_pmic_1: vu09_da9062@48 {
		compatible = "dlg,da9062";
		pinctrl-names = "default";
		pinctrl-0 = <&vu_pmic1_pins_default>;
		reg = <0x48>;
		gpio-controller;
		#gpio-cells = <2>;
		status = "okay";
		
		gpio {
                        compatible = "dlg,da9062-gpio";
                };
	};

        vu09_pmic_2: vu09_da9062@58 {
                compatible = "dlg,da9062";
                pinctrl-names = "default";
                pinctrl-0 = <&vu_pmic2_pins_default>;
                reg = <0x58>;
                gpio-controller;
                #gpio-cells = <2>;
                status = "okay";

                gpio {
                        compatible = "dlg,da9062-gpio";
                };
        };

		

};
&mcu_i2c1 {

	status = "disabled";
};

&main_sdhci0 {
	status = "okay";
	/* eMMC */
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	status = "okay";
	/* SD card */
	pinctrl-0 = <&main_mmc1_pins_default>;
	pinctrl-names = "default";
	vqmmc-supply = <&vdd_sd_dv>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	bus-width = <4>;
};

&serdes_ln_ctrl {
	status = "okay";
	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
};


&usb_serdes_mux {
	idle-states = <1>; /* USB0 to SERDES lane 3 */
};

&usbss0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss0_pins_default>;
	ti,vbus-divider;
	ti,usb2-only;
};

&usb0 {
	status = "okay";
	dr_mode = "host";
        phy-names = "cdns3,usb2-phy";
};

&tscadc0 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&serdes_refclk {
	clock-frequency = <100000000>;
};


&serdes_wiz0 {
	status = "okay";
};
&serdes0 {
	status = "okay";
	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
	};

	serdes0_usxgmii_link: phy@2 {
		reg = <2>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USXGMII>;
		resets = <&serdes_wiz0 3>;
	};
};

&pcie1_rc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_rst_pins_default>;
	reset-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>;
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
};



#define K3_TS_OFFSET(pa, val)  (0x4+(pa)*4) (0x10000 | val)

&timesync_router {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_cpts>;

	/* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */
	mcu_cpsw_cpts: mcu-cpsw-cpts {
		pinctrl-single,pins = <
			/* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */
			K3_TS_OFFSET(25, 17)
			>;
	};
};

&mcu_spi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi_pins_default>;
	ti,spi-num-cs = <4>;
	ti,pindir-d0-out-d1-in;
	tpm@3 {
		compatible = "tcg,tpm_tis-spi";
		reg = <3>;
		spi-max-frequency = <16000000>;
		lpcpd-gpios = <&main_gpio0 51 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};
};

Fullscreen marvell_10g.txt Download

diff -Naur --no-dereference A/drivers/net/phy/marvell10g.c B/drivers/net/phy/marvell10g.c
--- A/drivers/net/phy/marvell10g.c	2026-04-27 13:09:16.258744000 +0530
+++ B/drivers/net/phy/marvell10g.c	2026-04-27 15:00:38.968908000 +0530
@@ -25,6 +25,7 @@
 #include <linux/bitfield.h>
 #include <linux/ctype.h>
 #include <linux/delay.h>
+#include <linux/firmware.h>
 #include <linux/hwmon.h>
 #include <linux/marvell_phy.h>
 #include <linux/phy.h>
@@ -50,6 +51,14 @@
 	MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH	= 0x6,
 	MV_PMA_BOOT		= 0xc050,
 	MV_PMA_BOOT_FATAL	= BIT(0),
+	MV_PMA_BOOT_PRGS_MASK	= 0x0006,
+	MV_PMA_BOOT_PRGS_INIT	= 0x0000,
+	MV_PMA_BOOT_PRGS_WAIT	= 0x0002,
+	MV_PMA_BOOT_PRGS_CSUM	= 0x0004,
+	MV_PMA_BOOT_PRGS_JRAM	= 0x0006,
+	MV_PMA_BOOT_APP_STARTED	= BIT(4),
+	MV_PMA_BOOT_APP_LOADED	= BIT(6),
+
 
 	MV_PCS_BASE_T		= 0x0000,
 	MV_PCS_BASE_R		= 0x1000,
@@ -96,6 +105,13 @@
 	MV_PCS_PORT_INFO_NPORTS_MASK	= 0x0380,
 	MV_PCS_PORT_INFO_NPORTS_SHIFT	= 7,
 
+	/* Firmware downloading */
+	MV_PCS_FW_ADDR_LOW	= 0xd0f0,
+	MV_PCS_FW_ADDR_HIGH	= 0xd0f1,
+	MV_PCS_FW_DATA		= 0xd0f2,
+	MV_PCS_FW_CSUM		= 0xd0f3,
+
+
 	/* SerDes reinitialization 88E21X0 */
 	MV_AN_21X0_SERDES_CTRL2	= 0x800f,
 	MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS	= BIT(13),
@@ -148,6 +164,7 @@
 	int (*set_mactype)(struct phy_device *phydev, int mactype);
 	int (*select_mactype)(unsigned long *interfaces);
 	int (*init_interface)(struct phy_device *phydev, int mactype);
+	const char *firmware_path;
 
 #ifdef CONFIG_HWMON
 	int (*hwmon_read_temp_reg)(struct phy_device *phydev);
@@ -499,6 +516,134 @@
 	.module_insert = mv3310_sfp_insert,
 };
 
+struct mv3310_fw_hdr {
+	struct {
+		u32 size;
+		u32 addr;
+		u16 csum;
+	} __packed data;
+
+	u8 flags;
+#define MV3310_FW_HDR_DATA_ONLY BIT(6)
+
+	u8 port_skip;
+	u32 next_hdr;
+	u16 csum;
+
+	u8 pad[14];
+} __packed;
+
+
+
+static int mv3310_load_fw_sect(struct phy_device *phydev,
+			       const struct mv3310_fw_hdr *hdr, const u8 *data)
+{
+	int err = 0;
+	size_t i;
+	u16 csum;
+
+	dev_dbg(&phydev->mdio.dev, "Loading %u byte %s section at 0x%08x\n",
+		hdr->data.size,
+		(hdr->flags & MV3310_FW_HDR_DATA_ONLY) ? "data" : "executable",
+		hdr->data.addr);
+
+	for (i = 0, csum = 0; i < hdr->data.size; i++)
+		csum += data[i];
+
+	if ((u16)~csum != hdr->data.csum) {
+		dev_err(&phydev->mdio.dev, "Corrupt section data\n");
+		return -EINVAL;
+	}
+
+	phy_lock_mdio_bus(phydev);
+
+	/* Any existing checksum is cleared by a read */
+	__phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_FW_CSUM);
+
+	__phy_write_mmd(phydev, MDIO_MMD_PCS, MV_PCS_FW_ADDR_LOW,  hdr->data.addr & 0xffff);
+	__phy_write_mmd(phydev, MDIO_MMD_PCS, MV_PCS_FW_ADDR_HIGH, hdr->data.addr >> 16);
+
+	for (i = 0; i < hdr->data.size; i += 2) {
+		__phy_write_mmd(phydev, MDIO_MMD_PCS, MV_PCS_FW_DATA,
+				(data[i + 1] << 8) | data[i]);
+	}
+
+	csum = __phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_FW_CSUM);
+	if ((u16)~csum != hdr->data.csum) {
+		dev_err(&phydev->mdio.dev, "Download failed\n");
+		err = -EIO;
+		goto unlock;
+	}
+
+	if (hdr->flags & MV3310_FW_HDR_DATA_ONLY)
+		goto unlock;
+
+	__phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT, 0, MV_PMA_BOOT_APP_LOADED);
+	mdelay(200);
+	if (!(__phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT) & MV_PMA_BOOT_APP_STARTED)) {
+		dev_err(&phydev->mdio.dev, "Application did not startup\n");
+		err = -ENODEV;
+	}
+
+unlock:
+	phy_unlock_mdio_bus(phydev);
+	return err;
+}
+
+static int mv3310_load_fw(struct phy_device *phydev)
+{
+	const struct mv3310_chip *chip = to_mv3310_chip(phydev);
+	const struct firmware *fw;
+	struct mv3310_fw_hdr hdr;
+	const u8 *sect;
+	size_t i;
+	u16 csum;
+	int err;
+
+	if (!chip->firmware_path)
+		return -EOPNOTSUPP;
+
+	err = request_firmware(&fw, chip->firmware_path, &phydev->mdio.dev);
+	if (err)
+		return err;
+
+	if (fw->size & 1) {
+		err = -EINVAL;
+		goto release;
+	}
+
+	for (sect = fw->data; (sect + sizeof(hdr)) < (fw->data + fw->size);) {
+		memcpy(&hdr, sect, sizeof(hdr));
+		hdr.data.size = cpu_to_le32(hdr.data.size);
+		hdr.data.addr = cpu_to_le32(hdr.data.addr);
+		hdr.data.csum = cpu_to_le16(hdr.data.csum);
+		hdr.next_hdr = cpu_to_le32(hdr.next_hdr);
+		hdr.csum = cpu_to_le16(hdr.csum);
+
+		for (i = 0, csum = 0; i < offsetof(struct mv3310_fw_hdr, csum); i++)
+			csum += sect[i];
+
+		if ((u16)~csum != hdr.csum) {
+			dev_err(&phydev->mdio.dev, "Corrupt section header\n");
+			err = -EINVAL;
+			break;
+		}
+
+		err = mv3310_load_fw_sect(phydev, &hdr, sect + sizeof(hdr));
+		if (err)
+			break;
+
+		if (!hdr.next_hdr)
+			break;
+
+		sect = fw->data + hdr.next_hdr;
+	}
+
+release:
+	release_firmware(fw);
+	return err;
+}
+
 static int mv3310_probe(struct phy_device *phydev)
 {
 	const struct mv3310_chip *chip = to_mv3310_chip(phydev);
@@ -520,6 +665,13 @@
 		return -ENODEV;
 	}
 
+	if ((ret & MV_PMA_BOOT_PRGS_MASK) == MV_PMA_BOOT_PRGS_WAIT) {
+		ret = mv3310_load_fw(phydev);
+		if (ret)
+			return ret;
+	}
+
+
 	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
@@ -1164,6 +1316,7 @@
 	.set_mactype = mv3310_set_mactype,
 	.select_mactype = mv3310_select_mactype,
 	.init_interface = mv3310_init_interface,
+	.firmware_path = "mrvl/x3310fw.hdr",
 
 #ifdef CONFIG_HWMON
 	.hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
@@ -1428,4 +1581,5 @@
 };
 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");
+MODULE_FIRMWARE("mrvl/x3310fw.hdr");
 MODULE_LICENSE("GPL");

dmesg
-------------
root@j7200-iwg52m:~# dmesg | grep -i phy
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[ 0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[ 0.656771] phy-gmii-sel 40f04040.phy: phy_gmii_sel_init_ports 1
[ 0.656780] phy-gmii-sel 40f04040.phy: phy_gmii_init_phy field 4040 2 0
[ 0.656939] phy-gmii-sel 104044.phy: phy_gmii_sel_init_ports 4
[ 0.656943] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 4044 2 0
[ 0.656975] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 4048 2 0
[ 0.656999] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 404c 2 0
[ 0.657027] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 4050 2 0
[ 1.097623] wiz bus@100000:wiz@5060000: wiz_get_lane_phy_types: Lanes 0-1 have phy-type 2
[ 1.097629] wiz bus@100000:wiz@5060000: wiz_get_lane_phy_types: Lanes 2-2 have phy-type 12
[ 1.281821] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 1.281834] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 1.297690] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 1.297704] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 1.297822] davinci_mdio c000f00.mdio: phy[1]: device c000f00.mdio:01, driver unknown
[ 1.307597] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F-VD-CG Gigabit Ethernet
[ 1.335853] phy-gmii-sel 104044.phy: phy_gmii_sel_of_xlate id:1 ext:139780496
[ 1.993234] cdns-torrent-phy 5060000.serdes: Multi-link: PCIe (2 lanes) & USXGMII (1 lanes)
[ 2.137075] cdns-torrent-phy 5060000.serdes: Timeout waiting for CMN ready
[ 2.145678] phy phy-5060000.serdes.5: phy poweron failed --> -110
[ 2.153297] j721e-pcie-host 2910000.pcie: Failed to init phy
[ 2.271710] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 2.271738] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 2.288847] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 2.288864] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 2.289014] davinci_mdio c000f00.mdio: phy[1]: device c000f00.mdio:01, driver unknown
[ 2.298814] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F-VD-CG Gigabit Ethernet
[ 2.327117] phy-gmii-sel 104044.phy: phy_gmii_sel_of_xlate id:1 ext:139780496
[ 2.428046] cdns-torrent-phy 5060000.serdes: Timeout waiting for CMN ready
[ 2.436654] phy phy-5060000.serdes.6: phy poweron failed --> -110
root@j7200-iwg52m:~#
root@j7200-iwg52m:~#
root@j7200-iwg52m:~# dmesg | grep -i eth
[ 0.000000] psci: probing for conduit method from DT.
[ 0.811216] optee: probing for conduit method.
[ 1.231846] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00[0]'
[ 1.231858] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00[0]'
[ 1.281821] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 1.281834] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 1.297690] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 1.297704] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 1.307597] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F-VD-CG Gigabit Ethernet
[ 1.319998] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 5 quirks:00000000
[ 2.209256] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00[0]'
[ 2.209285] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00[0]'
[ 2.271710] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 2.271738] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 2.288847] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 2.288864] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 2.298814] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F-VD-CG Gigabit Ethernet
[ 2.311243] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 5 quirks:00000000
[ 2.445161] am65-cpsw-nuss: probe of c000000.ethernet failed with error -110
[ 4.133203] systemd[1]: /lib/systemd/system/bt-enable.service:9: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the sett.
[ 4.196773] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the s.
root@j7200-iwg52m:~#
root@j7200-iwg52m:~#
root@j7200-iwg52m:~# dmesg | grep -i wiz
[ 1.097577] wiz bus@100000:wiz@5060000: GPIO lookup for consumer typec-dir
[ 1.097584] wiz bus@100000:wiz@5060000: using device tree for GPIO lookup
[ 1.097591] of_get_named_gpiod_flags: can't parse 'typec-dir-gpios' property of node '/bus@100000/wiz@5060000[0]'
[ 1.097603] of_get_named_gpiod_flags: can't parse 'typec-dir-gpio' property of node '/bus@100000/wiz@5060000[0]'
[ 1.097612] wiz bus@100000:wiz@5060000: using lookup tables for GPIO lookup
[ 1.097616] wiz bus@100000:wiz@5060000: No GPIO consumer typec-dir found
[ 1.097623] wiz bus@100000:wiz@5060000: wiz_get_lane_phy_types: Lanes 0-1 have phy-type 2
[ 1.097629] wiz bus@100000:wiz@5060000: wiz_get_lane_phy_types: Lanes 2-2 have phy-type 12
root@j7200-iwg52m:~#
root@j7200-iwg52m:~# dmesg | grep -i pci
[ 0.093441] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[ 0.549104] PCI: CLS 0 bytes, default 64
[ 1.993234] cdns-torrent-phy 5060000.serdes: Multi-link: PCIe (2 lanes) & USXGMII (1 lanes)
[ 1.993792] j721e-pcie-host 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[ 2.003762] j721e-pcie-host 2910000.pcie: IO 0x0018001000..0x0018010fff -> 0x0018001000
[ 2.014436] j721e-pcie-host 2910000.pcie: MEM 0x0018011000..0x001fffffff -> 0x0018011000
[ 2.025110] j721e-pcie-host 2910000.pcie: IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[ 2.036277] j721e-pcie-host 2910000.pcie: GPIO lookup for consumer reset
[ 2.036290] j721e-pcie-host 2910000.pcie: using device tree for GPIO lookup
[ 2.036325] of_get_named_gpiod_flags: parsed 'reset-gpios' property of node '/bus@100000/pcie@2910000[0]' - status (0)
[ 2.153297] j721e-pcie-host 2910000.pcie: Failed to init phy
[ 2.160516] j721e-pcie-host: probe of 2910000.pcie failed with error -110
root@j7200-iwg52m:~#
root@j7200-iwg52m:~#
root@j7200-iwg52m:~#
root@j7200-iwg52m:~# zcat /proc/config.gz | grep -i marvell
# CONFIG_PATA_MARVELL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_MARVELL_PHY=y
CONFIG_MARVELL_10G_PHY=y
# CONFIG_MARVELL_88X2222_PHY is not set
CONFIG_WLAN_VENDOR_MARVELL=y
# Marvell media platform drivers
root@j7200-iwg52m:~#
root@j7200-iwg52m:~#
root@j7200-iwg52m:~#

Thanks and Regards,
Subashini

0 Doredla Sudheer Kumar 1 month ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Subashini N said:
Also, I connected phy1 to the 10G node, but I am still seeing the “unknown device” and timeout issues.

It seems like Marvel driver is not found corresponding to the PHY you are using.

Please reachout to Marvel for this.

In regards USXGMII, as shared in previous threads you are supposed to use the parent clock of 88 under serdes_wiz0 node as shown in below.

&serdes_wiz0 {
    assigned-clocks = <&k3_clks 292 85>;
    assigned-clock-parents = <&k3_clks 292 88>;
};

Can you please check with above.

Best Regards,
Sudheer

0 Subashini N 1 month ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

After adding the mentioned clock entries, also I am getting the same issue.

root@j7200-iwg52m:~# dmesg | grep -i phy
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[ 0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[ 0.656565] phy-gmii-sel 40f04040.phy: phy_gmii_sel_init_ports 1
[ 0.656573] phy-gmii-sel 40f04040.phy: phy_gmii_init_phy field 4040 2 0
[ 0.656727] phy-gmii-sel 104044.phy: phy_gmii_sel_init_ports 4
[ 0.656731] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 4044 2 0
[ 0.656764] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 4048 2 0
[ 0.656788] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 404c 2 0
[ 0.656817] phy-gmii-sel 104044.phy: phy_gmii_init_phy field 4050 2 0
[ 1.097848] wiz bus@100000:wiz@5060000: wiz_get_lane_phy_types: Lanes 0-1 have phy-type 2
[ 1.097854] wiz bus@100000:wiz@5060000: wiz_get_lane_phy_types: Lanes 2-2 have phy-type 12
[ 1.282037] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 1.282053] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 1.296929] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 1.296943] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 1.297058] davinci_mdio c000f00.mdio: phy[1]: device c000f00.mdio:01, driver unknown
[ 1.306832] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F-VD-CG Gigabit Ethernet
[ 1.335085] phy-gmii-sel 104044.phy: phy_gmii_sel_of_xlate id:1 ext:139780496
[ 2.020258] cdns-torrent-phy 5060000.serdes: Multi-link: PCIe (2 lanes) & USXGMII (1 lanes)
[ 2.163508] cdns-torrent-phy 5060000.serdes: Timeout waiting for CMN ready
[ 2.172123] phy phy-5060000.serdes.5: phy poweron failed --> -110
[ 2.179746] j721e-pcie-host 2910000.pcie: Failed to init phy
[ 2.295844] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 2.295869] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@3[0]'
[ 2.314388] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 2.314407] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/bus@100000/ethernet@c000000/mdio@f00/ethernet-phy@1[0]'
[ 2.314589] davinci_mdio c000f00.mdio: phy[1]: device c000f00.mdio:01, driver unknown
[ 2.324370] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F-VD-CG Gigabit Ethernet
[ 2.352762] phy-gmii-sel 104044.phy: phy_gmii_sel_of_xlate id:1 ext:139780496
[ 2.453202] cdns-torrent-phy 5060000.serdes: Timeout waiting for CMN ready
[ 2.461807] phy phy-5060000.serdes.6: phy poweron failed --> -110
root@j7200-iwg52m:~#
root@j7200-iwg52m:~#
root@j7200-iwg52m:~# dmesg | grep -i wiz
[ 1.097799] wiz bus@100000:wiz@5060000: GPIO lookup for consumer typec-dir
[ 1.097805] wiz bus@100000:wiz@5060000: using device tree for GPIO lookup
[ 1.097816] of_get_named_gpiod_flags: can't parse 'typec-dir-gpios' property of node '/bus@100000/wiz@5060000[0]'
[ 1.097828] of_get_named_gpiod_flags: can't parse 'typec-dir-gpio' property of node '/bus@100000/wiz@5060000[0]'
[ 1.097837] wiz bus@100000:wiz@5060000: using lookup tables for GPIO lookup
[ 1.097841] wiz bus@100000:wiz@5060000: No GPIO consumer typec-dir found
[ 1.097848] wiz bus@100000:wiz@5060000: wiz_get_lane_phy_types: Lanes 0-1 have phy-type 2
[ 1.097854] wiz bus@100000:wiz@5060000: wiz_get_lane_phy_types: Lanes 2-2 have phy-type 12
root@j7200-iwg52m:~#
root@j7200-iwg52m:~#
root@j7200-iwg52m:~# dmesg | grep -i torrent
[ 2.020258] cdns-torrent-phy 5060000.serdes: Multi-link: PCIe (2 lanes) & USXGMII (1 lanes)
[ 2.163508] cdns-torrent-phy 5060000.serdes: Timeout waiting for CMN ready
[ 2.453202] cdns-torrent-phy 5060000.serdes: Timeout waiting for CMN ready

root@j7200-iwg52m:~# cat /sys/kernel/debug/clk/clk_summary | grep -A20 -B5 serdes
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
5060000.serdes_refclk-rec 0 0 0 0 0 0 50000 N
5060000.serdes_refclk-der 0 0 0 0 0 0 50000 N
5060000.serdes_refclk-driver 0 0 0 0 0 0 50000 N
bus@100000:wiz@5060000_phy-en-refclk 0 0 0 0 0 0 50000 N
clk:292:89 1 1 0 100000000 0 0 50000 Y
bus@100000:wiz@5060000_pll1-refclk 1 1 0 100000000 0 0 50000 Y
clk:292:88 1 1 0 125000000 0 0 50000 Y
clk:292:85 1 1 0 156250000 0 0 50000 Y
bus@100000:wiz@5060000_refclk-dig 0 0 0 156250000 0 0 50000 Y
bus@100000:wiz@5060000_pll0-refclk 1 1 0 156250000 0 0 50000 Y
clk:292:87 0 0 0 0 0 0 50000 Y
clk:292:86 0 0 0 19200000 0 0 50000 Y
clk:292:11 0 0 0 125000000 0 0 50000 Y
clk:288:14 0 0 0 0 0 0 50000 Y
clk:288:13 0 0 0 19200000 0 0 50000 Y
clk:288:12 0 0 0 19200000 0 0 50000 Y
clk:288:3 0 0 0 24000000 0 0 50000 Y
clk:278:2 0 0 0 48000000 0 0 50000 Y
clk:275:4 1 1 0 50000000 0 0 50000 Y
clk:253:9 0 0 0 0 0 0 50000 Y
clk:253:8 0 0 0 0 0 0 50000 Y
clk:253:7 0 0 0 0 0 0 50000 Y
clk:253:6 0 0 0 0 0 0 50000 Y
--
clk:0:5 0 0 0 0 0 0 50000 Y
clk:0:4 0 0 0 58823529 0 0 50000 Y
clk:0:3 0 0 0 60000000 0 0 50000 Y
clk:0:2 0 0 0 19200000 0 0 50000 Y
clk:0:1 0 0 0 19200000 0 0 50000 Y
serdes-refclk 0 0 0 100000000 0 0 50000 Y
root@j7200-iwg52m:~#

Thanks and Regards,
Subashini

0 Doredla Sudheer Kumar 1 month ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

As I have mentioned earlier, you have to check with Marvell about unknown driver error for PHY
[ 2.314589] davinci_mdio c000f00.mdio: phy[1]: device c000f00.mdio:01, driver unknown

Subashini N said:
[ 2.453202] cdns-torrent-phy 5060000.serdes: Timeout waiting for CMN ready
[ 2.461807] phy phy-5060000.serdes.6: phy poweron failed --> -110

Regarding PHY power ON issue, could you please share the following SerDes register dump.

Base address : 5060000 and offset address are mentioned below.

Serdes TOP CTRL : 0x408

Reset: 0x40C

PLL lock status: 0xE000

LaneCTL0: 0x480 + (Lane number * 0x40) offset for each Lane

Lane Div: 0x484

Lane Allign: 0x488

Lane status: 0x48C

Best Regards,
Sudheer

0 Subashini N 1 month ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

Doredla Sudheer Kumar said:
Base address : 5060000 and offset address are mentioned below.

Serdes TOP CTRL : 0x408

Reset: 0x40C

PLL lock status: 0xE000

LaneCTL0: 0x480 + (Lane number * 0x40) offset for each Lane

Lane Div: 0x484

Lane Allign: 0x488

Lane status: 0x48C

Please find the register's value.

Serdes TOP CTRL
----------------
root@j7200-iwg52m:~# devmem2 0x5060408
/dev/mem opened.
Memory mapped at address 0xffff8416c000.
Read at address 0x05060408 (0xffff8416c408): 0x1C000000

Reset
-----
root@j7200-iwg52m:~# devmem2 0x506040C
/dev/mem opened.
Memory mapped at address 0xffffafdd9000.
Read at address 0x0506040C (0xffffafdd940c): 0x80000000

PLL lock status
----------------
root@j7200-iwg52m:~# devmem2 0x506E000
/dev/mem opened.
Memory mapped at address 0xffff94ca1000.
Read at address 0x0506E000 (0xffff94ca1000): 0x00820050

LaneCTL0
---------
root@j7200-iwg52m:~# devmem2 0x5060480
/dev/mem opened.
Memory mapped at address 0xffff8d5b1000.
Read at address 0x05060480 (0xffff8d5b1480): 0x70000000

root@j7200-iwg52m:~# devmem2 0x50604C0
/dev/mem opened.
Memory mapped at address 0xffff9bc36000.
Read at address 0x050604C0 (0xffff9bc364c0): 0x70000000

root@j7200-iwg52m:~# devmem2 0x5060500
/dev/mem opened.
Memory mapped at address 0xffffa671e000.
Read at address 0x05060500 (0xffffa671e500): 0x713800C0

root@j7200-iwg52m:~# devmem2 0x50605A0
/dev/mem opened.
Memory mapped at address 0xffff8343b000.
Read at address 0x050605A0 (0xffff8343b5a0): 0x00000000

Lane Div
--------
root@j7200-iwg52m:~# devmem2 0x5060484
/dev/mem opened.
Memory mapped at address 0xffffb2a4e000.
Read at address 0x05060484 (0xffffb2a4e484): 0x00000000

Lane Allign
-----------
root@j7200-iwg52m:~# devmem2 0x5060488
/dev/mem opened.
Memory mapped at address 0xffff9b331000.
Read at address 0x05060488 (0xffff9b331488): 0x00000000

Lane status
------------
root@j7200-iwg52m:~# devmem2 0x506048C
/dev/mem opened.
Memory mapped at address 0xffff8e032000.
Read at address 0x0506048C (0xffff8e03248c): 0x00000002
root@j7200-iwg52m:~#

Thanks and Regards,

Subashini

0 Doredla Sudheer Kumar 1 month ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Let me review the register dump and get back to you on Monday.

Best Regards,
Sudheer

0 Subashini N 1 month ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

Greetings of the day.

Could you please share any input on this?

Thanks and Regards,

Subashini

0 Doredla Sudheer Kumar 1 month ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

From the Logs I can see only SerDes PLL1 is locked but not PLL0. Also, SerDes is not ready.

Will check on our side and get back to you.

Best Regards,
Sudheer

0 Subashini N 1 month ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

As per your recommendation, I have used the 11.02.00.04 SDK version. I used standalone compilation and copied the image and dtb file to the ext4 rootfs in the SD card and booted. While booting, I am getting the below error, and then the board is hanging.

[ 0.793739] sdhci: Secure Digital Host Controller Interface driver
[ 0.800067] sdhci: Copyright(c) Pierre Ossman
[ 0.804636] sdhci-pltfm: SDHCI platform and OF driver helper
[ 0.810769] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....

Thanks and Regards,
Subashini

0 Doredla Sudheer Kumar 1 month ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Subashini N said:
As per your recommendation, I have used the 11.02.00.04 SDK version. I used standalone compilation and copied the image and dtb file to the ext4 rootfs in the SD card and booted. While booting, I am getting the below error, and then the board is hanging.

Have you take care of your device tree changes made on top of SDK 9.2 to SDK 11.2 while migrating?

Best Regards,
Sudheer

0 Subashini N 1 month ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

HI Sudheer,

I have updated all the sources to the latest version, but I am now facing a booting issue. Since debugging this will take some time, can we continue using SDK version 09.02.00.04 for now? In the meantime, could you please help us resolve the PLL locking issue on this version?

Thanks and Regards,
Subashini

0 Doredla Sudheer Kumar 1 month ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Understood, let me try to run the same on my side with SDK 9.2 and update you by end of tomorrow.

Best Regards,
Sudheer

0 Subashini N 1 month ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

Greetings of the day.

Did you get any chance to look into this issue? Could you please share any input on this?

Thanks and Regards,

Subashini

0 Doredla Sudheer Kumar 1 month ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

Subashini N said:
Did you get any chance to look into this issue? Could you please share any input on this?

We are also getting driver fail with default SDK due to unsupported PHY mode, as USXGMII was not supported out of box SDK.

We are checking on our side with above suggested driver changes and update you soon.

Best Regards,
Sudheer

0 Subashini N 27 days ago in reply to Doredla Sudheer Kumar

Prodigy 40 points

Hi Sudheer,

Hope you are doing well.

Did you get any chance to look into this issue? Could you suggest any workarounds to resolve this issue?

Thanks and Regards,
subashini

0 Doredla Sudheer Kumar 27 days ago in reply to Subashini N

TI__Guru* 79310 points

Hi,

We are actively working on this, were facing some issue with SerDes PLL configuration.

Will post you an update once we were able to test it on our side.

Best Regards,
Sudheer

0 Doredla Sudheer Kumar 22 days ago in reply to Doredla Sudheer Kumar

TI__Guru* 79310 points

Hi,

Can you try to disable PCIe and check USXGMII alone working or not using the below patches along with above USXGMII Mode support change as captured below.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_j7200_2D00_evm_2D00_usxgmii_2D00_exp1.dtso

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/usxgmii_5F00_j7200.patch

We have tired SerDes PLL lock is success and the clock is set to 156.25MHz.

Best Regards,
Sudheer