Part Number: DRA821U
Hi,
We have a new revision (B) of our custom board based on the DRA821U. Previously, we posted about the bring-up of revision A HERE.
At the moment, we are uploading the boot stage through MCU_UART. Specifically, we are loading tiboot3.bin, and we are encountering the same issue as before:
U-Boot SPL 2025.01-ti-gac2433f99366-dirty (Oct 06 2025 - 12:51:40 +0200)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Timeout during frequency handshake
### ERROR ### Please RESET the board ###
In this revision, we are using the following DDR part number: MT53E512M32D1ZW-046 WT:B.
For DDR configuration, we are using the file k3-j7200-ddr-pnt-lp4.zip which worked correctly in revision A with the DDR part number MT53E512M32D1ZW-046 AUT:B. We reused the same configuration file for revision B; however, it is not working with the MT53E512M32D1ZW-046 WT:B device. This configuration file was generated as a result of the discussion in the previous post where we encountered the same issue.
We also attempted to reduce both boot and operating frequencies to check whether DDR training would succeed at lower speeds, but the result remained the same.
We would appreciate your guidance on the following points:
- How can we verify whether the DDR is functioning correctly?
- What messages or behavior should we expect if the DDR is not detected?
- Assuming the DDR configuration file is correct, what debugging methods are recommended to further investigate the DDR initialization process and identify the root cause?
Thank in advance,
Santi
