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TDA4VM: MDIO Protocol Overview and Timing Design Considerations

Manisha Narayana Gowda
Intellectual 380 points

Part Number: TDA4VM
Other Parts Discussed in Thread: DRA829,

Hello Experts,

We are using the J721E (DRA829 / TDA4VM / AM68P) processor in conjunction with Marvell Alaska PHY devices (88EA1517 / 88EA1512 and 88E1548P). Currently, I am performing a timing analysis to determine the optimal MDC clock width, taking into account the minimum values of internal delays, setup time, hold time, and clock period.

So far, the analysis has focused on the MDIO write path (CPU to PHY), where the PHY setup and hold time requirements are considered while selecting the MDC timing parameters. However, I would like clarification regarding the MDIO read path (PHY to CPU). Specifically, when data is driven by the PHY and sampled by the processor, should the processor’s MDIO input setup and hold timing requirements, as specified in the processor datasheet, also be included in the timing analysis?

Any additional insights or best practices for MDC clock period selection that account for both read and write paths would be greatly appreciated.

Kind regards
Thank You

Manisha Narayana

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  • 0
    TI__Guru 64160 points

    Hi Manisha Narayana,

    Yes, the requirements from the datasheet must be taken into account while running the timing requirements; especially the input setup and hold time. We have usually not seen issues as long as the timing margins are maintained in a practical system application. It assumes that the max round trip PCB delay of 10ns; and with RT delays less than that should not have issues and gives margin to the timing.  

  • 0 in reply to ShreyasRao
    Intellectual 380 points

    Hi Shreyas,

    During reading the data sent from PHY,  I do consider the PHY internal delay which is 0-20ns and propagation delay of 0-5 ns, 
    Once the data is already valid on MDIO data line does the set up time of CPU side contributes anything to reading the non corrupted data?
    if yes can you please explain how does set up time on CPU still matters to read the Data which is already placed by PHY on MDIO line  (after obeying PHY internal delay and propagation delay)

    Regards

    ShreyasRao said:
    RT delays less than that should not have issues and gives margin to the timing.  

    What is RT delays?/

  • 0 in reply to Manisha Narayana Gowda
    TI__Guru 64160 points

    Hi Manisha,

    The setup and hold time must be met for the input side as mentioned in the timing conditions on the datasheet. The data must be valid before the clock samples the line and must not toggle during or immediately before /after sampling. As long as they adhere to the MDIO industry standard specs this is unlikely. RT referred to the round trip delay. 

  • 0 in reply to ShreyasRao
    TI__Guru 64160 points

    It would be ideal if the timing simulation can be done during the schematic / layout phase before the board is sent out to fab to know it is functional. For slow speed interface such as the MDIO there are usually no issues meeting the timing specs.