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AM62A7-Q1: AM62A7-Q1 power down sequence

shihui xu
Prodigy 170 points

Part Number: AM62A7-Q1
Other Parts Discussed in Thread: TPS6593-Q1

We are using the combination of AM62A7-Q1 and TPS6593, but I have a question about the power down sequence:

From the DS of AM62A7-Q1(page97-98) I found the power-down sequencing to be like the picture  below.  Does this mean after we pulling down MCU_PORz, we can directly shut down the VSYS(3.3V) voltage regulator without informing TPS6593 first? 

  1. image.png
  • 0
    TI__Mastermind 27766 points

    Hi,

    Thanks for reaching out. What is "VSYS(3.3V)" in your design? If you are referring to the pre-regulator that is connected to the PMIC input supply pins, then it must stay ON with a valid voltage level until the PMIC completes the power-down sequence (not only until PORz goes low).  

    Thanks,

    Brenda

  • 0
    Prodigy 170 points

    Hi Brenda,

    This is the definition of VSYS from page94 of the ds, which I think have the same meaning from your reply:

    Does this mean that Waveform A in the above image is incorrect?

    And can you point out the normal power down routine (from “mission state” to “no supply”) on the state diagram below? Do I have to send an off request to transit the device state to LP STANDBY first before shutdown the pre-regulator of PMIC input supply? As shown in the state diagram, all states can transition normally to the “BACKUP” and “NO SUPPLY” states as long as the voltage reaches the threshold.

  • 0 in reply to shihui xu
    TI__Mastermind 27766 points

    Hi,

    The TPS6593-Q1 PMIC is configurable. To understand how the power states were configured along with the corresponding triggers, I recommend referring to the user guide or apps note for the specific OPN that your application uses. For example, if your application uses TPS65931211RWERQ1 (PMIC OPN used on AM62A EVM), the user guide can be found at he following link: https://www.ti.com/lit/pdf/slvucm3  

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Prodigy 170 points

    Hi Brenda,

    Actually I've already read this user guide, but the state machine didn't even include a "No supply" state. I am now using the combination of AM62A7-Q1 and TPS65931211RWERQ1 (PMIC OPN used on AM62A EVM). The question is very simple. I just need a normal power-down procedure. What must I do from the moment I decide to start shutting down until before turning off the VSYS (3V3) input (which from my understanding, is the no supply state for both pmic and soc).

  • +1 in reply to shihui xu
    TI__Mastermind 27766 points

    The normal orderly power-down sequence can be triggered by hardware (pulling the enable pin low) or by software (TRIGGER_I2C_0=1). The pre-regulator can be turned-OFF only after the power-down sequence is complete.  

    From the TPS65931211-Q1 user guide:

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Prodigy 170 points

    Thanks for your reply.

    Another thing that confuses me is that from the power-down timing waveform J&K, it can be seen that after PORz is asserted, the external crystal is still oscillating, which seems a bit strange. Meanwhile I find them blank in the BALL STATE DURING RESET roll in the Pin Attributes Table.

    image.png

  • 0 in reply to shihui xu
    TI__Mastermind 27766 points

    Hi,

    Not sure if I understand the concern here. MCU_OSC is the input of the high frequency oscillator. It is NOT the actual HFOSC0_CLKOUT that goes to the clocking architecture. It would stop clocking whenever the corresponding supply drops below a valid voltage level. For example, the AM62A EVM uses an external oscillator that is supplied by VDDA_1P8. If you check the power-down sequence, the MCU_OSC_XI goes low around the time VDDA_1P8 drops. 

    Thanks,

    Brenda