TDA4VEN-Q1: TDA4VEN C7X Clock Startup Initialization Fault

Hi Qiang Leo,

Could you please check this thread which has the similar failure:
e2echina.ti.com/.../tda4ven-q1-tda4ven-q1-j722s-c7x-may-get-stuck-writing-mrr-registers-during-ipc-initialization

Qiang Leo said:

After troubleshooting, we found that the program gets stuck at SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, 2) within the Dpl_init() function when the startup fails.

The hang at SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, 2) may be a software boot-order race condition. When Linux (A53) brings up remoteproc / rpmsg, it sends an IPC message into the C7x mailbox FIFO before the C7x has finished Dpl_init. Since the C7x mailbox interrupt is level-triggered through the CLEC, the pending message keeps the interrupt line continuously asserted with no ISR registered yet, causing the C7x to hang at its first off-chip bus access.

Could you please try drain all pending mailbox FIFOs (MAILBOX_MESSAGE) until MAILBOX_MSGSTATUS is zero and clear MAILBOX_IRQSTATUS_CLR before proceeding with Dpl_init on the C7x side.
On the Linux side, ensure no rpmsg messages are sent to C7x until the C7x firmware has posted its RPMSG_NS_CREATE announcement, not just on RPROC_RUNNING.

Could you also confirm your Processor SDK RTOS and MCU+ SDK versions, and whether Linux remoteproc is active before C7x starts?

Regards,
Shabary S Sundar

Hi Shabary S Sundar,

Thanks for your reply. I followed your instructions and checked the mailbox status before executing the Dpl_init function. The code is as follows, but the freezing issue still hasn't been resolved. Did I write the code incorrectly, or do I need to modify it together with the ARM side?If I need to modify the ARM-side code, how should I make the changes here?

The SDK RTOS version I am using is 10.0.0.05, and the MCU SDK version is 10.0.0.25.

Hi Qiang Leo,

Qiang Leo said:

I followed your instructions and checked the mailbox status before executing the Dpl_init function.

Could you confirm exactly where IpcNotify_clearMailboxFifo_C7x() is invoked? Can you try running it as the first thing in main() before Dpl_init() is entered.

Could you also try to use the IpcNotify_mailboxDisableInt() primitive (defined in source/drivers/ipc_notify/v0/ipc_notify_v0_mailbox.h) to mask the mailbox interrupt before draining, so that new messages arriving during the drain cannot re-assert the interrupt line.

Regards,
Shabary S Sundar

Hi Shabary S Sundar,

I have placed both the interrupt disable and interrupt status clear operations at the very start of the Dpl_init() function. However, the system still gets stuck. Note that Dpl_init() is the first function executed in main(). Could this issue actually not be caused by the interrupt itself?

Regards,

Qiang Leo

Hi Shabary S Sundar,

I clicked 'This resolved my issue' by mistake. This issue is NOT resolved. Could you continue to provide assistance?

Hi Qiang Leo,

Qiang Leo said:

Is this caused by the firewall or PSC issue you mentioned earlier?

Could you please confirm whether the C7x is released from reset by SBL on R5F, or by Linux remoteproc on the A53 after Linux is up? If Linux is involved, please share the UART boot log up to the hang along with.

Qiang Leo said:

found that the C7x core hangs when reading the JTAG ID register, and this phenomenon occurs every single time

Could you also try to add a CPU busy-wait at the very start of Dpl_init(), before the JTAGID read.

volatile uint32_t i;
for (i = 0; i < 100000000U; i++) {
__asm__ __volatile__("nop");
}

Regards,
Shabary S Sundar

Hi Shabary S Sundar,

Shabary S Sundar said:

Could you also try to add a CPU busy-wait at the very start of Dpl_init(), before the JTAGID read.

It still hangs every time it starts up.Perhaps the JTAGID register is simply not supposed to be accessed.

Shabary S Sundar said:

Could you please confirm whether the C7x is released from reset by SBL on R5F, or by Linux remoteproc on the A53 after Linux is up? If Linux is involved, please share the UART boot log up to the hang along with.

The C7x core is released from reset by the R5F SBL.

Hi Qiang Leo,

Could you please drop the JTAGID read for now and keep only the CPU delay right before the original SOC_controlModuleUnlockMMR() call. 

Qiang Leo said:

The C7x core is released from reset by the R5F SBL.

Can you also confirm whether you have made any changes to the SBL bootflow? Are you using the stock SBL from the MCU+ SDK 10.0.0.25  or a customized one?

Regards,
Shabary S Sundar

Hi Shabary S Sundar,

Shabary S Sundar said:

Could you please drop the JTAGID read for now and keep only the CPU delay right before the original SOC_controlModuleUnlockMMR() call. 

I drop the JTAGID read for now and keep only the CPU delay right before the original SOC_controlModuleUnlockMMR() call. 

This will definitely cause the program to get stuck at SOC_controlModuleUnlockMMR() every single time.

Shabary S Sundar said:

Can you also confirm whether you have made any changes to the SBL bootflow? Are you using the stock SBL from the MCU+ SDK 10.0.0.25  or a customized one?

Perhaps I didn't make myself clear earlier. Actually, the DSP firmware is loaded by U-Boot during the U-Boot boot phase. This U-Boot is compiled from the official original source code without any modifications. Below are the Linux boot logs. We have removed the R5 firmware, so the R5 cores remain inactive. Although the log indicates the C7x is connected, in fact the C7x core fails to start properly.

Qiang Leo said:

Although the log indicates the C7x is connected, in fact the C7x core fails to start properly

Hi Qiang Leo,

A few quick points and one test that should isolate the cause.

On your dmesg: 78000000.r5f is the WKUP R5F running DM, loaded by U-Boot SPL via tispl.bin — that's expected and required, not a user R5F. Your MCU R5F (0x79000000) and Main R5F (0x78400000) are correctly inactive. So DM is alive and TISCI is working.

On the hang address: 0x00100014 is inside MAIN_CTRL_MMR0, not JTAGID. The real JTAGID on J722S is at 0x43000014 (WKUP_CTRL_MMR0). SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, 2) writes KICK0 at 0x00109008.

On the 100M NOP delay making it 100% reproducible: a delay worsening the failure indicates another agent in the system (most likely Linux remoteproc attach) is changing state during the window — closing C7x's access to MAIN_CTRL_MMR0. Since you boot C7x from U-Boot (not the WKUP R5F SBL), the full firewall/clock setup that SBL normally does may not be performed.

Could you please run this test:

1. Reproduce the hang.
2. Halt C7x_1 via CCS over JTAG.
3. From CCS Memory Browser, read these two addresses:
   • 0x43000014 — real JTAGID (WKUP domain)
   • 0x00100000 — start of MAIN_CTRL_MMR0
4. Share both values.

Regards,
Shabary S Sundar

Hi Shabary S Sundar,

I encountered a problem where I was unable to read memory using the Memory Browser in CCS, so I switched to using the devmem2 command instead.

1. I checked the values at these two addresses using the md command in U-Boot and the devmem2 command in Linux respectively. The value at address 0x00100000 is 0x61800215, and the value at address 0x43000014 is 0x0bba002f. The values at these two addresses remain the same whether the C7x is suspended or not.

2. During the C7x boot process, I wrote the values from addresses 0x00100000 and 0x43000014 into shared memory. I observed that the C7x occasionally gets stuck at the stage where it reads the value from address 0x00100000. Combined with the known issue of unlocking MMR registers, I am wondering whether the C7x loses read/write permissions to the MMR register region when it enters a suspended state.

Regards,

Qiang Leo

Hi Qiang Leo,

To confirm whether this is a firewall issue, please follow the steps below to collect TIFS trace logs.

Step 1 — Enable TIFS Trace in Board Config

In your U-Boot source tree, edit board/ti/j722s/board-cfg.yaml:

- trace_dst_enables: 0x00
- trace_src_enables: 0x00
+ trace_dst_enables: 0x0D
+ trace_src_enables: 0x3F

trace_dst_enables: 0x0D enables UART + ITM (JTAG) + Memory buffer output. trace_src_enables: 0x3F enables all trace sources including security/firewall operations.

Note: Enabling trace has a performance impact. Use only for debug.

Step 2 — Rebuild U-Boot and Flash

# From your U-Boot build directory
make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- j722s_evm_a53_defconfig
make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu-

Copy the generated tispl.bin to your SD card boot partition, replacing the existing one:

cp tispl.bin /media/<your-sd-card>/boot/
sync

The trace config is baked into tispl.bin and sent to TIFS via TISCI_MSG_BOARD_CONFIG early in SPL — there is no way to enable it at runtime, a rebuild is required.

Step 3 — Reproduce the Hang

Boot the board normally. Let Linux come up fully and let remoteproc load and attach the C7x firmware. 

Important: Once the hang occurs, do not power cycle the board. The TIFS trace buffer lives in on-chip SRAM and will be lost on power-off or reset. Leave the board in the hung state and proceed immediately to Step 4.

Step 4 — Connect CCS and Dump the Trace Buffer

Connect your JTAG/CCS to the board while it is in the hung state.

In CCS Memory Browser:

1. Connect to the A53 core (or any available core)
2. Open View → Memory Browser
3. Enter address 0x4405F000
4. Right-click → Save Memory
5. Set length to 0x1000 (4096 bytes)
6. Save as a .bin or .hex file

Alternatively, using the CCS Scripting Console:

mem.savebin("tifs_trace.bin", 0x4405F000, 0x1000);

J722S TIFS trace buffer: Base = 0x4405F000, Size = 0x1000 bytes (per TI TISCI documentation).

Step 5 — Also Capture devmem2 Reads Before and After Attach

While at it, from the A53 terminal, please capture the following at two points:

Before Linux remoteproc attaches C7x (early in boot):

devmem2 0x00100000 w    # MAIN_CTRL_MMR0 PID — confirms A53 access
devmem2 0x43000014 w    # WKUP_CTRL_MMR0 JTAGID — confirms WKUP access

After C7x hang occurs (A53 is still alive):

devmem2 0x00100000 w    # If this still reads OK from A53, confirms only C7x is blocked

This cross-check confirms the firewall is selectively blocking C7x master ID and not A53.

Step 6 — Share the Following Results:

1. The tifs_trace.bin dump from 0x4405F000
2. The devmem2 outputs from Step 5
3. Your full dmesg output showing the remoteproc attach sequence

Any TISCI_MSG_SET_FWL_REGION (message ID 0x9000) call targeting the MAIN_CTRL_MMR0 firewall region (0x00100000–0x00107FFF) that is issued during Linux remoteproc attach and does not include the C7x master ID (privId 32/33) in the permission list. This would confirm that Linux is dynamically narrowing the MAIN_CTRL_MMR0 firewall after C7x firmware starts, causing C7x to silently hang when it tries to access that region inside SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, 2).

Please share the outputs and will analyze further.

You can also refer the following tisci document:  https://software-dl.ti.com/tisci/esd/latest/4_trace/trace.html#trace-memory-buffer-location

Regards,
Shabary S Sundar

Hi Shabary S Sundar,

Shabary S Sundar said:

The tifs_trace.bin dump from 0x4405F000

After reproducing the C7x hang issue, I read the value at address 0x4405F000 via CCS and saved the data to tifs_trace.bin. It turns out all contents in this file are zero.

Shabary S Sundar said:

The devmem2 outputs from Step 5

Hi Qiang Leo,

Qiang Leo said:

After reproducing the C7x hang issue, I read the value at address 0x4405F000 via CCS and saved the data to tifs_trace.bin. It turns out all contents in this file are zero.

Could you confirm if the modified board-cfg.yaml was rebuilt into a fresh signed boardcfg blob inside tispl.bin (or the rebuilt binary was flashed)?
To get a valid trace, a full clean rebuild of U-Boot (make mrproper then full build) is needed so the new YAML is regenerated into the signed blob.

Qiang Leo said:

However, this approach fails to reproduce the C7x hang issue. I suspect that pausing U-Boot countdown alters the boot timing sequence, which allows the C7x firmware to load normally.

 The C7x firmware needs to write one register — TIMER1_CLKSEL at 0x001081B4 — to set its OS-tick timer source. This register sits inside a firewall-protected region (MAIN_CTRL_MMR0 partition 2).
Can we move this single register write from C7x to U-Boot. U-Boot runs on A53, which always has full access to MAIN_CTRL_MMR0. The timer mux is configured before C7x ever starts.

Change 1: In U-Boot

Add to board_late_init() in board/ti/j722s/evm.c (runs after TISCI is up, before rproc start c7x):

/* Pre-configure TIMER1_CLKSEL for C7x */
writel(0x68EF3490, 0x00109008);   /* MMR0 partition 2 KICK0 unlock */
writel(0xD172BC5A, 0x0010900C);   /* MMR0 partition 2 KICK1 unlock */
writel(0x0,        0x001081B4);   /* TIMER1_CLKSEL = HFOSC0_CLKOUT */
writel(0x0,        0x00109008);   /* re-lock partition 2 */
writel(0x0,        0x0010900C);

This writes the timer mux from A53 (which has firewall access) before C7x ever runs.

Change 2: In C7x firmware

In the SysConfig-generated ti_dpl_config.c for the C7x core, remove the now-redundant write from Dpl_init():

// SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, 2);
// *(volatile uint32_t*)(TIMER1_CLOCK_SRC_MUX_ADDR) = TIMER1_CLOCK_SRC_HFOSC0_CLKOUT;
// SOC_controlModuleLockMMR(SOC_DOMAIN_ID_MAIN, 2);

ClockP_init() (called immediately after) will see the already-configured TIMER1 mux and proceed normally

Regards,
Shabary S Sundar

Hi Shabary S Sundar,

Shabary S Sundar said:

Could you confirm if the modified board-cfg.yaml was rebuilt into a fresh signed boardcfg blob inside tispl.bin

To ensure the changes take effect fully, we have deleted the entire build folder after modifying board-cfg.yaml. Nevertheless, when the C7x hang issue is reproduced, all values read from address 0x4405F000 are still zero.

Shabary S Sundar said:

Add to board_late_init() in board/ti/j722s/evm.c

Recompiled U-Boot with the above modifications, but the C7x hang issue still persists. This time the core gets stuck inside ClockP_init(). The value read from address 0x4405F000 remains zero. The values of other addresses captured via CCS are shown in the figure below:

All the addresses mentioned above are physical addresses.

Regards,

Qiang Leo

Hi Qiang Leo,

Qiang Leo said:

Recompiled U-Boot with the above modifications, but the C7x hang issue still persists. This time the core gets stuck inside ClockP_init().

Let me take a look into this and will get back to you.

Regards,
Shabary S Sundar

Hi Qiang Leo,

Qiang Leo said:

he value read from address 0x4405F000 remains zero. The values of other addresses captured via CCS are shown in the figure below:

Could you please try to connect to the WKUP R5F core in CCS and re-dump 0x4405F000 length 0x1000? Also can you try to call Board_init from C7x and check?

Regards,
Shabary S Sundar

Hi Shabary S Sundar,

Shabary S Sundar said:

Could you please try to connect to the WKUP R5F core in CCS and re-dump 0x4405F000 length 0x1000?

We have performed connection tests targeting physical addresses, and all readbacks return zero. Could you advise whether we need to replace tiboot3 and uboot.img simultaneously?

Shabary S Sundar said:

Also can you try to call Board_init from C7x and check?

The implementation of the Board_init() function on the C7x side is empty.

It is possible that there is a mismatch with my SDK version; I am using SDK 10.0.0.8(ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08).

Regards,

Qiang Leo

Hi Qiang Leo,
The engineer responsible is currently out of office. Please expect a day delay in response.
Regards,
Ben

Hi Qiang Leo,

Qiang Leo said:

Could you advise whether we need to replace tiboot3 and uboot.img simultaneously?

Yes, you can replace tiboot3.bin, tispl.bin, and u-boot.img together when you modify any of board-cfg.yaml, sec-cfg.yaml, pm-cfg.yaml, or rm-cfg.yaml.

Regards,
Shabary S Sundar

Hi Shabary S Sundar,

I have reproduced the C7x hang issue and saved the register contents at address 0x4405F000 into the file tifs_trace.bin. Screenshots of the relevant logs are attached below.

Regards,

Qiang Leo

Hi Qiang Leo,

Qiang Leo said:

I have reproduced the C7x hang issue and saved the register contents at address 0x4405F000 into the file tifs_trace.bin. Screenshots of the relevant logs are attached below.

Thanks for the logs, let me go through them in detail and will get back to you. Just to be clear before obtaining the TIFS trace, you have reverted all the debug steps we have previously applied, this trace belongs to the original code which caused hang right?

Regards,
Shabary S Sundar

Hi Shabary S Sundar,

Yes, I have removed the previous debug configurations.Looking forward to your reply.

Regards,

Qiang Leo

Hi Qiang Leo,

Can you share the traces in the text format so that we can parse them.

Regards
Diwakar

Hi Diwakar,

I have converted the trace data into a TXT file as follows.

0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 36 30 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 36 38 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 36 43 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 37 34 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 37 43 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 38 30 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 38 38 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 39 30 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 39 38 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 39 43 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 41 34 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 41 43 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 42 30 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 42 38 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 43 30 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 43 38 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 43 43 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 44 34 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 44 43 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 45 30 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 45 38 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 46 30 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 46 38 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 46 43 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 42 30 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 42 38 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 42 43 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 43 34 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 43 43 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 44 30 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 44 38 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 45 30 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 45 38 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 45 43 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 46 34 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 46 43 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 32 38 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 32 43 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 33 30 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 33 38 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 33 43 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34
0a 0a 45 78 63 65 70 74 69 6f 6e 20 61 64 64 72
20 20 30 78 34 35 42 30 30 30 30 30 0a 46 57 4c
20 45 78 63 65 70 74 69 6f 6e 20 20 30 78 31 30
32 30 31 30 30 0a 20 30 78 33 30 30 30 30 0a 20
30 78 35 45 46 34 34 0a 20 30 78 30 0a 20 30 78
46 46 38 31 41 44 34 0a 20 30 78 34 0a 0a 45 78
63 65 70 74 69 6f 6e 20 61 64 64 72 20 20 30 78
34 35 42 30 30 30 30 30 0a 46 57 4c 20 45 78 63
65 70 74 69 6f 6e 20 20 30 78 31 30 32 30 31 30
30 0a 20 30 78 33 30 30 30 30 0a 20 30 78 35 45
46 34 43 0a 20 30 78 30 0a 20 30 78 46 46 38 31
41 44 34 0a 20 30 78 34 0a 0a 45 78 63 65 70 74
69 6f 6e 20 61 64 64 72 20 20 30 78 34 35 42 30
30 30 30 30 0a 46 57 4c 20 45 78 63 65 70 74 69
6f 6e 20 20 30 78 31 30 32 30 31 30 30 0a 20 30
78 33 30 30 30 30 0a 20 30 78 35 45 46 35 34 0a
20 30 78 30 0a 20 30 78 46 46 38 31 41 44 34 0a
20 30 78 34 0a 0a 45 78 63 65 70 74 69 6f 6e 20
61 64 64 72 20 20 30 78 34 35 42 30 30 30 30 30
0a 46 57 4c 20 45 78 63 65 70 74 69 6f 6e 20 20
30 78 31 30 32 30 31 30 30 0a 20 30 78 33 30 30
30 30 0a 20 30 78 35 45 46 35 38 0a 20 30 78 30
0a 20 30 78 46 46 38 31 41 44 34 0a 20 30 78 34

Regards,

Qiang Leo

Hi Qiang Leo

Hi Diwakar,

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF60
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF68
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF6C
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF74
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF7C
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF80
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF88
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF90
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF98
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF9C
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFA4
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFAC
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFB0
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFB8
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFC0
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFC8
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFCC
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFD4
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFDC
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFE0
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFE8
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFF0
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFF8
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFFC
 0x0
 0xFF81AD4
 0x4

1020100
 0x30000
 0x5EFB0
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFB8
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFBC
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFC4
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFCC
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFD0
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFD8
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFE0
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFE8
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFEC
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFF4
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EFFC
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF28
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF2C
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF30
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF38
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF3C
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF44
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF4C
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF54
 0x0
 0xFF81AD4
 0x4

Exception addr  0x45B00000
FWL Exception  0x1020100
 0x30000
 0x5EF58
 0x0
 0xFF81AD4
 0x4

Regards,

Qiang Leo

Hi Qiang Leo

Hi Diwakar,

Yes. The C7x core hangs intermittently in the function SOC_controlModuleUnlockMMR() during boot. Following the advice from the technical support engineer, I enabled the two debug configurations: trace_dst_enables and trace_src_enables. After that, I connected to the R5 core on the board via USB and captured the memory logs using CCS.

Regards,

Qiang Leo

Qiang Leo said:

Yes. The C7x core hangs intermittently in the function SOC_controlModuleUnlockMMR() during boot. Following the advice from the technical support engineer, I enabled the two debug configurations: trace_dst_enables and trace_src_enables. After that, I connected to the R5 core on the board via USB and captured the memory logs using CCS.

The memory range which we need to look into is 0x4405F000 to 0x4406F000, if we are crossing this boundary and looking into TIFS memory we will get exception.

Regards
Diwakar

Hi Diwakar,

The address I accessed is indeed 0x4405F000 with a length of 0x1000. I also viewed data beyond this address range in the CCS Memory View. Could this have triggered the exception?

Regards,

Qiang Leo

Hi Qiang Leo